Add aiecc flag for basic_alloc_scheme

Xilinx · Apr 24, 2024 · 9fd6b84 · 9fd6b84
1 parent 28c0de4
commit 9fd6b84
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Showing 9 changed files with 42 additions and 12 deletions.
diff --git a/python/compiler/aiecc/cl_arguments.py b/python/compiler/aiecc/cl_arguments.py
@@ -264,6 +264,13 @@ def parse_args(args=None):
         default="0x901",
         help="Kernel id in xclbin file",
     )
+    parser.add_argument(
+        "--basic-alloc-scheme",
+        dest="basic_alloc_scheme",
+        default=False,
+        action="store_const",
+        help="Use basic memory allocation scheme for AIE buffer address assignment",
+    )
 
     opts = parser.parse_args(args)
     return opts

diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py
@@ -35,7 +35,7 @@
 from aie.ir import Context, Location, Module
 from aie.passmanager import PassManager
 
-INPUT_WITH_ADDRESSES_PIPELINE = (
+INPUT_WITH_SWITCHBOXES_PIPELINE = (
     Pipeline()
     .lower_affine()
     .add_pass("aie-canonicalize-device")
@@ -50,7 +50,6 @@
         .add_pass("aie-lower-broadcast-packet")
         .add_pass("aie-create-packet-flows")
         .add_pass("aie-lower-multicast")
-        .add_pass("aie-assign-buffer-addresses"),
     )
     .convert_scf_to_cf()
 )
@@ -986,15 +985,39 @@ async def run_flow(self):
                 "[green] MLIR compilation:", total=1, command="1 Worker"
             )
 
-            file_with_addresses = self.prepend_tmp("input_with_addresses.mlir")
-            pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE.materialize(module=True)
+            file_with_switchboxes = self.prepend_tmp("input_with_switchboxes.mlir")
+            pass_pipeline = INPUT_WITH_SWITCHBOXES_PIPELINE.materialize(module=True)
             run_passes(
                 pass_pipeline,
                 self.mlir_module_str,
-                file_with_addresses,
+                file_with_switchboxes,
                 self.opts.verbose,
             )
 
+            file_with_addresses = self.prepend_tmp("input_with_addresses.mlir")
+            if opts.basic_alloc_scheme:
+                await self.do_call(
+                    progress_bar.task,
+                    [
+                        "aie-opt",
+                        "--aie-assign-buffer-addresses=basic-alloc",
+                        file_with_switchboxes,
+                        "-o",
+                        file_with_addresses,
+                    ],
+                )
+            else:
+                await self.do_call(
+                    progress_bar.task,
+                    [
+                        "aie-opt",
+                        "--aie-assign-buffer-addresses",
+                        file_with_switchboxes,
+                        "-o",
+                        file_with_addresses,
+                    ],
+                )
+
             cores = generate_cores_list(await read_file_async(file_with_addresses))
             t = do_run(
                 [

diff --git a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
+// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
 module @benchmark01_DDR_SHIM_fill_rate {

diff --git a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
+// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
 module @benchmark_02_LM2DDR {

diff --git a/test/benchmarks/03_Flood_DDR/aie.mlir b/test/benchmarks/03_Flood_DDR/aie.mlir
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
+// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
 // RUN: %run_on_board ./test.elf
 
 module @benchmark03_Flood_DDR {

diff --git a/test/npu-xrt/add_256_using_dma_op_no_double_buffering/run.lit b/test/npu-xrt/add_256_using_dma_op_no_double_buffering/run.lit
@@ -7,7 +7,7 @@
 // RUN: aie-translate --aie-generate-cdo aie.mlir.prj/input_physical.mlir
 // RUN: cp *.elf aie.mlir.prj/
 // RUN: cp *.bin aie.mlir.prj/
-// RUN: %python aiecc.py --no-aiesim --aie-generate-npu --aie-generate-xclbin --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
+// RUN: %python aiecc.py --no-aiesim --aie-generate-npu --aie-generate-xclbin --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
 // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++
 // RUN: %run_on_npu ./test.exe aie.xclbin | FileCheck %s
 // CHECK: PASS!
diff --git a/test/npu-xrt/add_314_using_dma_op/run.lit b/test/npu-xrt/add_314_using_dma_op/run.lit
@@ -7,7 +7,7 @@
 // RUN: aie-translate --aie-generate-cdo aie.mlir.prj/input_physical.mlir
 // RUN: cp *.elf aie.mlir.prj/
 // RUN: cp *.bin aie.mlir.prj/
-// RUN: %python aiecc.py --no-aiesim --aie-generate-npu --aie-generate-xclbin --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
+// RUN: %python aiecc.py --no-aiesim --aie-generate-npu --aie-generate-xclbin --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
 // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++
 // RUN: %run_on_npu ./test.exe aie.xclbin | FileCheck %s
 // CHECK: PASS!

diff --git a/test/npu-xrt/add_one_using_dma/run.lit b/test/npu-xrt/add_one_using_dma/run.lit
@@ -3,7 +3,7 @@
 //
 // REQUIRES: ryzen_ai
 //
-// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
+// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
 // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
 // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
 // CHECK: PASS!

diff --git a/test/npu-xrt/matrix_multiplication_using_dma/run.lit b/test/npu-xrt/matrix_multiplication_using_dma/run.lit
@@ -4,7 +4,7 @@
 // REQUIRES: ryzen_ai, chess
 //
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/mm.cc -o ./mm.o
-// RUN: %python aiecc.py --xbridge --aie-generate-cdo --aie-generate-npu --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
+// RUN: %python aiecc.py --xbridge --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir
 // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
 // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s
 // CHECK: PASS!