Add basic AIE2 tests.

test/unit_tests/aie2/00_itsalive/aie.mlir

@@ -0,0 +1,27 @@
+//===- aie.mlir ------------------------------------------------*- MLIR -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2021 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+// RUN: aiecc.py --no-unified %s
+// RUN: aiecc.py --unified    %s
+
+module @test00_itsalive {
+  AIE.device(xcve2802) {
+    %tile12 = AIE.tile(1, 3)
+
+    %buf12_0 = AIE.buffer(%tile12) { sym_name = "a", address = 0 } : memref<256xi32>
+
+    %core12 = AIE.core(%tile12) {
+      %val1 = arith.constant 1 : i32
+      %idx1 = arith.constant 3 : index
+      %2 = arith.addi %val1, %val1 : i32
+      AIE.end
+    }
+  }
+}

test/unit_tests/aie2/01_precompiled_core_function/aie.mlir

@@ -0,0 +1,38 @@
+//===- aie.mlir ------------------------------------------------*- MLIR -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2021 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+// RUN: clang --target=aie2 -c %S/kernel.cc
+// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
+// RUN: %run_on_board ./test.elf
+
+// CHECK: PASS!
+
+module @test_chesss_01_precompiled_core_function {
+  AIE.device(xcve2802) {
+    %tile13 = AIE.tile(1, 3)
+
+    %buf13_0 = AIE.buffer(%tile13) { sym_name = "a" } : memref<256xi32>
+    %buf13_1 = AIE.buffer(%tile13) { sym_name = "b" } : memref<256xi32>
+
+    %lock13_3 = AIE.lock(%tile13, 3) { sym_name = "input_lock" }
+    %lock13_5 = AIE.lock(%tile13, 5) { sym_name = "output_lock" }
+
+    func.func private @func(%A: memref<256xi32>, %B: memref<256xi32>) -> ()
+
+    %core13 = AIE.core(%tile13) {
+      AIE.useLock(%lock13_3, "Acquire", 1) // acquire for read(e.g. input ping)
+      AIE.useLock(%lock13_5, "Acquire", 0) // acquire for write
+      func.call @func(%buf13_0, %buf13_1) : (memref<256xi32>, memref<256xi32>) -> ()
+      AIE.useLock(%lock13_3, "Release", 0) // release for write
+      AIE.useLock(%lock13_5, "Release", 1) // release for read
+      AIE.end
+    } { link_with="kernel.o" }
+  }
+}

test/unit_tests/aie2/01_precompiled_core_function/kernel.cc

@@ -0,0 +1,20 @@
+//===- kernel.cc ------------------------------------------------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2021 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+#include "kernel.h"
+
+void func(int32_t *a, int32_t *b) {
+  int val = a[3];
+  int val2 = val + val;
+  val2 += val;
+  val2 += val;
+  val2 += val;
+  b[5] = val2;
+}

test/unit_tests/aie2/01_precompiled_core_function/kernel.h

@@ -0,0 +1,15 @@
+//===- kernel.h -------------------------------------------------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2021 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+// #include <stdio.h>
+
+extern "C" {
+void func(int32_t *a, int32_t *b);
+}

test/unit_tests/aie2/01_precompiled_core_function/test.cpp

@@ -0,0 +1,74 @@
+//===- test.cpp -------------------------------------------------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2020 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+#include "test_library.h"
+#include <cassert>
+#include <cmath>
+#include <cstdio>
+#include <cstring>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <thread>
+#include <unistd.h>
+#include <xaiengine.h>
+
+#include "aie_inc.cpp"
+
+int main(int argc, char *argv[]) {
+  printf("test start.\n");
+
+  aie_libxaie_ctx_t *_xaie = mlir_aie_init_libxaie();
+  mlir_aie_init_device(_xaie);
+
+  mlir_aie_clear_tile_memory(_xaie, 1, 3);
+
+  mlir_aie_configure_cores(_xaie);
+  mlir_aie_configure_switchboxes(_xaie);
+  mlir_aie_configure_dmas(_xaie);
+  mlir_aie_initialize_locks(_xaie);
+
+  int errors = 0;
+
+  printf("Acquire input buffer lock first.\n");
+  mlir_aie_acquire_input_lock(_xaie, 0, 0); // Should this part of setup???
+  mlir_aie_write_buffer_a(_xaie, 3, 7);
+
+  printf("Start cores\n");
+  mlir_aie_start_cores(_xaie);
+
+  mlir_aie_check("Before release lock:", mlir_aie_read_buffer_b(_xaie, 5), 0,
+                 errors);
+
+  printf("Release input buffer lock.\n");
+  mlir_aie_release_input_lock(_xaie, 1, 0);
+
+  printf("Waiting to acquire output lock for read ...\n");
+  if (mlir_aie_acquire_output_lock(_xaie, 1, 1000)) {
+    errors++;
+    printf("ERROR: Failed to acquire output lock!\n");
+  }
+
+  mlir_aie_check("After release lock:", mlir_aie_read_buffer_b(_xaie, 5), 35,
+                 errors);
+
+  int res = 0;
+  if (!errors) {
+    printf("PASS!\n");
+    res = 0;
+  } else {
+    printf("Fail!\n");
+    res = -1;
+  }
+  mlir_aie_deinit_libxaie(_xaie);
+
+  printf("test done.\n");
+  return res;
+}

test/unit_tests/aie2/03_cascade_core_functions/aie.mlir

@@ -0,0 +1,46 @@
+//===- aie.mlir ------------------------------------------------*- MLIR -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2021 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+// RUN: clang --target=aie2 -c %S/kernel.cc
+// RUN: aiecc.py %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf
+// RUN: %run_on_board ./test.elf
+
+// CHECK: PASS!
+
+module {
+  AIE.device(xcve2802) {
+    %tile13 = AIE.tile(1, 3)
+    %tile23 = AIE.tile(2, 3)
+
+    %buf13_0 = AIE.buffer(%tile13) { sym_name = "a" } : memref<256xi32>
+    %buf23_0 = AIE.buffer(%tile23) { sym_name = "c" } : memref<256xi32>
+
+    %lock13_3 = AIE.lock(%tile13, 3) { sym_name = "input_lock" } // input buffer lock
+    %lock23_7 = AIE.lock(%tile23, 7) { sym_name = "output_lock" } // output buffer lock
+
+    func.func private @do_mul(%A: memref<256xi32>) -> ()
+    func.func private @do_mac(%A: memref<256xi32>) -> ()
+
+    %core13 = AIE.core(%tile13) {
+      AIE.useLock(%lock13_3, AcquireGreaterEqual, 1) // acquire for read(e.g. input ping)
+      func.call @do_mul(%buf13_0) : (memref<256xi32>) -> ()
+      AIE.end
+    } { link_with="kernel.o" }
+
+    %core23 = AIE.core(%tile23) {
+  //    %val1 = arith.constant 7 : i32
+  //    %idx1 = arith.constant 0 : index
+  //    memref.store %val1, %buf14_0[%idx1] : memref<256xi32>
+      func.call @do_mac(%buf23_0) : (memref<256xi32>) -> ()
+      AIE.useLock(%lock23_7, Release, 1) // release for read
+      AIE.end
+    } { link_with="kernel.o" }
+  }
+}

test/unit_tests/aie2/03_cascade_core_functions/kernel.cc

@@ -0,0 +1,64 @@
+//===- kernel13.cc ----------------------------------------------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2021 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+// #include <stdio.h>
+/*
+extern "C" void do_mul(int32_t *buf)
+{
+    int tmp = buf[3];
+    int val = tmp + 1;
+    v8acc48 v8acc;
+    v8int16 v8;
+    v8 = upd_elem(v8,0,val);
+    v8acc = ups(v8,0);
+    put_mcd(v8acc);
+}
+*/
+extern "C" void do_mul(int32_t *buf) {
+  int tmp = buf[3];
+  int val = tmp + tmp;
+  val += tmp;
+  val += tmp;
+  val += tmp;
+  buf[4] = val;
+  v32acc32 v8acc;
+  v32int16 v8;
+  v8 = upd_elem(v8, 0, (short)val);
+  put_mcd(v8);
+}
+/*
+extern "C" void do_mac(int32_t *buf)
+{
+    buf[0] = 17;
+    int tmp = ext_elem(srs(get_scd(),0),0);
+    buf[5] = tmp;
+}
+*/
+extern "C" void do_mac(int32_t *buf) {
+  buf[4] = 0;
+  v32int16 v8 = get_scd_v32int16();
+  int tmp = ext_elem(v8, 0);
+  buf[4] = tmp;
+  int val = tmp + tmp;
+  val += tmp;
+  val += tmp;
+  val += tmp;
+  buf[5] = val;
+}
+
+#ifdef TEST
+int32_t buf[32];
+
+int main() {
+  do_mul(buf);
+  do_mac(buf);
+  // printf("test is %d\n",buf[8]);
+}
+#endif

test/unit_tests/aie2/03_cascade_core_functions/test.cpp

@@ -0,0 +1,79 @@
+//===- test.cpp -------------------------------------------------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2020 Xilinx Inc.
+//
+//===----------------------------------------------------------------------===//
+
+#include "test_library.h"
+#include <cassert>
+#include <cmath>
+#include <cstdio>
+#include <cstring>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <sys/mman.h>
+#include <thread>
+#include <unistd.h>
+#include <xaiengine.h>
+
+#include "aie_inc.cpp"
+
+int main(int argc, char *argv[]) {
+  printf("test start.\n");
+
+  aie_libxaie_ctx_t *_xaie = mlir_aie_init_libxaie();
+  mlir_aie_init_device(_xaie);
+
+  mlir_aie_configure_cores(_xaie);
+  mlir_aie_configure_switchboxes(_xaie);
+  mlir_aie_configure_dmas(_xaie);
+  mlir_aie_initialize_locks(_xaie);
+
+  // FIXME: model in MLIR
+  XAie_CoreConfigAccumulatorControl(&(_xaie->DevInst), XAie_TileLoc(1, 3), WEST,
+                                    EAST);
+  XAie_CoreConfigAccumulatorControl(&(_xaie->DevInst), XAie_TileLoc(2, 3), WEST,
+                                    EAST);
+  int errors = 0;
+
+  mlir_aie_write_buffer_a(_xaie, 3, 7);
+
+  printf("Start cores\n");
+  mlir_aie_start_cores(_xaie);
+
+  // mlir_aie_check("Before release lock:", mlir_aie_read_buffer_c(_xaie, 5), 0,
+  //                errors);
+
+  printf("Release input buffer lock.\n");
+  mlir_aie_release_input_lock(_xaie, 1, 0);
+
+  printf("Waiting to acquire output lock for read ...\n");
+  if (mlir_aie_acquire_output_lock(_xaie, 1, 1000)) {
+    errors++;
+    printf("ERROR: Failed to acquire output lock!\n");
+  }
+
+  mlir_aie_check("After acquire lock:", mlir_aie_read_buffer_a(_xaie, 4), 35,
+                 errors);
+  mlir_aie_check("After acquire lock:", mlir_aie_read_buffer_c(_xaie, 4), 35,
+                 errors);
+  mlir_aie_check("After acquire lock:", mlir_aie_read_buffer_c(_xaie, 5), 175,
+                 errors);
+
+  int res = 0;
+  if (!errors) {
+    printf("PASS!\n");
+    res = 0;
+  } else {
+    printf("Fail!\n");
+    res = -1;
+  }
+  mlir_aie_deinit_libxaie(_xaie);
+
+  printf("test done.\n");
+  return res;
+}