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AIE2 shim DMA unit_tests
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These tests currently don't work:  The simulator behaves oddly,
sometimes hanging, sometimes reporting illegal addresses.
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@stephenneuendorffer
stephenneuendorffer committed Jul 24, 2023
1 parent fb068d0 commit ef549f4
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Showing 7 changed files with 158 additions and 211 deletions.
14 changes: 7 additions & 7 deletions test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/aie.mlir
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Original file line number Diff line number Diff line change
Expand Up @@ -21,10 +21,10 @@

module @test_chess_04_deprecated_shim_dma_precompiled_kernel{
AIE.device(xcve2802) {
%t73 = AIE.tile(7, 3)
%t72 = AIE.tile(7, 2)
%t71 = AIE.tile(7, 1)
%t70 = AIE.tile(7, 0)
%t73 = AIE.tile(3, 3)
%t72 = AIE.tile(3, 2)
%t71 = AIE.tile(3, 1)
%t70 = AIE.tile(3, 0)

%buf_a_ping = AIE.buffer(%t73) {sym_name = "a_ping" } : memref<256xi32>
%buf_a_pong = AIE.buffer(%t73) {sym_name = "a_pong" } : memref<256xi32>
Expand All @@ -42,7 +42,7 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{
%m73 = AIE.mem(%t73) {
%srcDma = AIE.dmaStart("S2MM", 0, ^bd0, ^dma0)
^dma0:
%dstDma = AIE.dmaStart("MM2S", 1, ^bd2, ^end)
%dstDma = AIE.dmaStart("MM2S", 0, ^bd2, ^end)
^bd0:
AIE.useLock(%lock_a_write, AcquireGreaterEqual, 1)
AIE.dmaBd(<%buf_a_ping : memref<256xi32>, 0, 256>, 0)
Expand Down Expand Up @@ -86,12 +86,12 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{
AIE.dmaStart(S2MM, 0, ^bd1, ^end)
^bd0:
AIE.useLock(%lock1_read, AcquireGreaterEqual, 1)
AIE.dmaBd(<%buffer_in : memref<512 x i32>, 0, 512>, 0)
AIE.dmaBd(<%buffer_in : memref<512 x i32>, 0, 8>, 0)
AIE.useLock(%lock1_write, Release, 1)
AIE.nextBd ^bd0
^bd1:
AIE.useLock(%lock2_write, AcquireGreaterEqual, 1)
AIE.dmaBd(<%buffer_out : memref<512 x i32>, 0, 512>, 0)
AIE.dmaBd(<%buffer_out : memref<512 x i32>, 0, 8>, 0)
AIE.useLock(%lock2_read, Release, 1)
AIE.nextBd ^bd1
^end:
Expand Down
18 changes: 9 additions & 9 deletions test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/kernel.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -35,15 +35,15 @@ extern "C" void core_7_3() {
int bounds = 2; // iter;

while (bounds > 0) {
acquire_greater_equal(A_READ, 1);
acquire_greater_equal(B_WRITE, 1);
if ((bounds & 0x1) == 0) {
func(a_ping, b_ping);
} else {
func(a_pong, b_pong);
}
release(A_WRITE, 1);
release(B_READ, 1);
// acquire_greater_equal(A_READ, 1);
// acquire_greater_equal(B_WRITE, 1);
// if ((bounds & 0x1) == 0) {
// func(a_ping, b_ping);
// } else {
// func(a_pong, b_pong);
// }
// release(A_WRITE, 1);
// release(B_READ, 1);
bounds--;
}
}
161 changes: 74 additions & 87 deletions test/unit_tests/chess_compiler_tests_aie2/04_shim_dma_kernel/test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -48,44 +48,18 @@ int main(int argc, char *argv[]) {
// mlir_aie_release_input_lock_read(_xaie, 1, 0);
// mlir_aie_release_output_lock_write(_xaie, 1, 0);

for (int bd = 0; bd < 16; bd++) {
// Take no prisoners. No regerts
// Overwrites the DMA_BDX_Control registers
for (int ofst = 0; ofst < 0x14; ofst += 0x4) {
u32 rb = mlir_aie_read32(_xaie, mlir_aie_get_tile_addr(_xaie, 7, 0) +
0x0001D000 + (bd * 0x14) + ofst);
if (rb != 0) {
printf("Before : bd%d_%x control is %08X\n", bd, ofst, rb);
}
// mlir_aie_write32(TileInst[7][0].TileAddr +
// 0x0001D000+(bd*0x14)+ofst, 0x0);
}
}

for (int dma = 0; dma < 4; dma++) {
for (int ofst = 0; ofst < 0x8; ofst += 0x4) {
u32 rb = mlir_aie_read32(_xaie, mlir_aie_get_tile_addr(_xaie, 7, 0) +
0x0001D140 + (dma * 0x8) + ofst);
if (rb != 0) {
printf("Before : dma%d_%x control is %08X\n", dma, ofst, rb);
}
// mlir_aie_write32(TileInst[7][0].TileAddr +
// 0x0001D140+(dma*0x8)+ofst, 0x0);
}
}
mlir_aie_print_shimdma_status(_xaie, 3, 0);

mlir_aie_initialize_locks(_xaie);

u32 sleep_u = 100000;
usleep(sleep_u);
printf("before DMA config\n");
mlir_aie_print_tile_status(_xaie, 7, 3);
mlir_aie_print_tile_status(_xaie, 3, 3);

mlir_aie_configure_dmas(_xaie);

usleep(sleep_u);
printf("after DMA config\n");
mlir_aie_print_tile_status(_xaie, 7, 3);
mlir_aie_print_tile_status(_xaie, 3, 3);
mlir_aie_print_dma_status(_xaie, 3, 3);

int errors = 0;

Expand All @@ -104,22 +78,31 @@ int main(int argc, char *argv[]) {
}
}
*/
#define DMA_COUNT 512
#define DMA_COUNT 16
ext_mem_model_t buf0, buf1;
int *ddr_ptr_in = mlir_aie_mem_alloc(buf0, DMA_COUNT);
int *ddr_ptr_out = mlir_aie_mem_alloc(buf1, DMA_COUNT);
for (int i = 0; i < DMA_COUNT; i++) {
*(ddr_ptr_in + i) = i + 1;
*(ddr_ptr_out + i) = 0;
}
mlir_aie_sync_mem_dev(buf0);
mlir_aie_sync_mem_dev(buf1);
// mlir_aie_sync_mem_dev(buf0);
// mlir_aie_sync_mem_dev(buf1);

printf("input: %lx %p\n", buf0.physicalAddr, ddr_ptr_in);
printf("output: %lx %p\n", buf1.physicalAddr, ddr_ptr_out);

mlir_aie_external_set_addr_input_buffer((u64)ddr_ptr_in);
mlir_aie_external_set_addr_output_buffer((u64)ddr_ptr_out);
mlir_aie_configure_shimdma_70(_xaie);
#ifdef __AIESIM__
mlir_aie_external_set_addr_input_buffer(buf0.physicalAddr);
mlir_aie_external_set_addr_output_buffer(buf1.physicalAddr);
#else
mlir_aie_external_set_addr_input_buffer((u64)ddr_ptr_in);
mlir_aie_external_set_addr_output_buffer((u64)ddr_ptr_out);
#endif
mlir_aie_configure_shimdma_30(_xaie);
// mlir_aie_print_shimdma_status(_xaie, 3, 0);

mlir_aie_clear_tile_memory(_xaie, 7, 3);
mlir_aie_clear_tile_memory(_xaie, 3, 3);

mlir_aie_acquire_input_lock_write(_xaie, -1, 0);
// Set iteration to 2 TODO: fix this
Expand Down Expand Up @@ -151,37 +134,41 @@ int main(int argc, char *argv[]) {
shimdma_stat_s2mm0);
*/

usleep(sleep_u);
printf("before core start\n");
mlir_aie_print_tile_status(_xaie, 7, 3);
// mlir_aie_print_tile_status(_xaie, 3, 3);
// mlir_aie_print_dma_status(_xaie, 3, 3);
// mlir_aie_print_shimdma_status(_xaie, 3, 0);

printf("Start cores\n");
// printf("Start cores\n");
mlir_aie_start_cores(_xaie);

usleep(sleep_u);
printf("after core start\n");
mlir_aie_print_tile_status(_xaie, 7, 3);
mlir_aie_print_shimdma_status(_xaie, 7, 0);
// mlir_aie_print_tile_status(_xaie, 3, 3);
// mlir_aie_print_dma_status(_xaie, 3, 3);
// mlir_aie_print_shimdma_status(_xaie, 3, 0);

printf("Release lock for accessing DDR.\n");
mlir_aie_release_input_lock_read(_xaie, 1, 0);

usleep(sleep_u);

if (mlir_aie_acquire_output_lock_read(_xaie, -1, 0)) {
errors++;
}

printf("after lock release\n");
mlir_aie_print_tile_status(_xaie, 7, 3);
mlir_aie_print_shimdma_status(_xaie, 7, 0);

mlir_aie_check("After", mlir_aie_read_buffer_a_ping(_xaie, 3), 4, errors);
mlir_aie_check("After", mlir_aie_read_buffer_a_pong(_xaie, 3), 256 + 4,
errors);
mlir_aie_check("After", mlir_aie_read_buffer_b_ping(_xaie, 5), 20, errors);
mlir_aie_check("After", mlir_aie_read_buffer_b_pong(_xaie, 5), (256 + 4) * 5,
errors);
// usleep(10000)
mlir_aie_release_input_lock_read(_xaie, 1, 10000);
// mlir_aie_print_dma_status(_xaie, 3, 3);
mlir_aie_print_shimdma_status(_xaie, 3, 0);

// // block waiting for result
// if (mlir_aie_acquire_output_lock_read(_xaie, -1, 10000)) {
// errors++;
// }

// printf("after lock release\n");
// mlir_aie_print_tile_status(_xaie, 3, 3);
// mlir_aie_print_dma_status(_xaie, 3, 3);
// mlir_aie_print_shimdma_status(_xaie, 3, 0);

// mlir_aie_check("After", mlir_aie_read_buffer_a_ping(_xaie, 3), 4, errors);
// mlir_aie_check("After", mlir_aie_read_buffer_a_pong(_xaie, 3), 256 + 4,
// errors);
// mlir_aie_check("After", mlir_aie_read_buffer_b_ping(_xaie, 5), 20, errors);
// mlir_aie_check("After", mlir_aie_read_buffer_b_pong(_xaie, 5), (256 + 4) * 5,
// errors);

/*
// Dump contents of ddr_ptr_out
Expand All @@ -191,7 +178,7 @@ int main(int argc, char *argv[]) {
printf("ddr_ptr_out[%d] = %d\n", i, d);
}
*/
mlir_aie_sync_mem_cpu(buf1);
// mlir_aie_sync_mem_cpu(buf1);
mlir_aie_check("DDR out", ddr_ptr_out[5], 20, errors);
mlir_aie_check("DDR out", ddr_ptr_out[256 + 5], (256 + 4) * 5, errors);

Expand All @@ -203,31 +190,31 @@ int main(int argc, char *argv[]) {
XAIE_DISABLE, XAIE_DISABLE); XAieDma_ShimChControl((&ShimDmaInst1),
XAIEDMA_SHIM_CHNUM_S2MM0, XAIE_DISABLE, XAIE_DISABLE, XAIE_DISABLE);
*/
for (int bd = 0; bd < 16; bd++) {
// Take no prisoners. No regerts
// Overwrites the DMA_BDX_Control registers
for (int ofst = 0; ofst < 0x14; ofst += 0x4) {
// u32 rb = mlir_aie_read32(TileInst[7][0].TileAddr +
// 0x0001D000+(bd*0x14)+ofst); printf("Before : bd%d_%x control is
// %08X\n", bd, ofst, rb);
mlir_aie_write32(_xaie,
mlir_aie_get_tile_addr(_xaie, 7, 0) + 0x0001D000 +
(bd * 0x14) + ofst,
0x0);
}
}

for (int dma = 0; dma < 4; dma++) {
for (int ofst = 0; ofst < 0x8; ofst += 0x4) {
// u32 rb = mlir_aie_read32(TileInst[7][0].TileAddr +
// 0x0001D140+(dma*0x8)+ofst); printf("Before : dma%d_%x control is
// %08X\n", dma, ofst, rb);
mlir_aie_write32(_xaie,
mlir_aie_get_tile_addr(_xaie, 7, 0) + 0x0001D140 +
(dma * 0x8) + ofst,
0x0);
}
}
// for (int bd = 0; bd < 16; bd++) {
// // Take no prisoners. No regerts
// // Overwrites the DMA_BDX_Control registers
// for (int ofst = 0; ofst < 0x14; ofst += 0x4) {
// // u32 rb = mlir_aie_read32(TileInst[7][0].TileAddr +
// // 0x0001D000+(bd*0x14)+ofst); printf("Before : bd%d_%x control is
// // %08X\n", bd, ofst, rb);
// mlir_aie_write32(_xaie,
// mlir_aie_get_tile_addr(_xaie, 3, 0) + 0x0001D000 +
// (bd * 0x14) + ofst,
// 0x0);
// }
// }

// for (int dma = 0; dma < 4; dma++) {
// for (int ofst = 0; ofst < 0x8; ofst += 0x4) {
// // u32 rb = mlir_aie_read32(TileInst[7][0].TileAddr +
// // 0x0001D140+(dma*0x8)+ofst); printf("Before : dma%d_%x control is
// // %08X\n", dma, ofst, rb);
// mlir_aie_write32(_xaie,
// mlir_aie_get_tile_addr(_xaie, 3, 0) + 0x0001D140 +
// (dma * 0x8) + ofst,
// 0x0);
// }
// }

int res = 0;
if (!errors) {
Expand Down
12 changes: 2 additions & 10 deletions test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/aie.mlir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -101,16 +101,8 @@ module @test_chess_04_deprecated_shim_dma_precompiled_kernel{
%lock2_read = AIE.lock(%t70, 4) {sym_name = "output_lock_read" }

// Shim DMA connection to kernel
AIE.flow(%t71, "South" : 3, %t73, "DMA" : 0)
AIE.flow(%t73, "DMA" : 1, %t71, "South" : 2)
%sw1 = AIE.switchbox(%t70) {
AIE.connect<"South" : 3, "North" : 3>
AIE.connect<"North" : 2, "South" : 2>
}
%mux1 = AIE.shimmux (%t70) {
AIE.connect<"DMA" : 0, "North" : 3>
AIE.connect<"North" : 2, "DMA" : 0>
}
AIE.flow(%t70, "DMA" : 3, %t73, "DMA" : 0)
AIE.flow(%t73, "DMA" : 1, %t70, "DMA" : 2)

// Shim DMA loads large buffer to local memory
%dma = AIE.shimDMA(%t70) {
Expand Down
32 changes: 7 additions & 25 deletions test/unit_tests/chess_compiler_tests_aie2/05_shim_dma_core_function/test.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,18 +31,6 @@ int main(int argc, char *argv[]) {
aie_libxaie_ctx_t *_xaie = mlir_aie_init_libxaie();
mlir_aie_init_device(_xaie);

/*
XAieDma_Shim ShimDMAInst_7_0;
XAieDma_ShimInitialize(&(TileInst[7][0]), &ShimDMAInst_7_0);
XAieDma_ShimChResetAll(&ShimDMAInst_7_0);
XAieDma_ShimBdClearAll(&ShimDMAInst_7_0);
XAieDma_Tile TileDmaInst_7_3;
XAieDma_TileInitialize(&(TileInst[7][3]), &TileDmaInst_7_3);
XAieDma_TileBdClearAll(&TileDmaInst_7_3);
XAieDma_TileChResetAll(&TileDmaInst_7_3);
*/

mlir_aie_configure_cores(_xaie);
mlir_aie_configure_switchboxes(_xaie);
// mlir_aie_release_input_lock_read(_xaie, 1, 0);
Expand Down Expand Up @@ -76,14 +64,11 @@ int main(int argc, char *argv[]) {

mlir_aie_initialize_locks(_xaie);

u32 sleep_u = 100000;
usleep(sleep_u);
printf("before DMA config\n");
mlir_aie_print_tile_status(_xaie, 7, 3);

mlir_aie_configure_dmas(_xaie);

usleep(sleep_u);
printf("after DMA config\n");
mlir_aie_print_tile_status(_xaie, 7, 3);

Expand Down Expand Up @@ -115,8 +100,13 @@ int main(int argc, char *argv[]) {
mlir_aie_sync_mem_dev(buf0);
mlir_aie_sync_mem_dev(buf1);

mlir_aie_external_set_addr_input_buffer((u64)ddr_ptr_in);
mlir_aie_external_set_addr_output_buffer((u64)ddr_ptr_out);
#ifdef __AIESIM__
mlir_aie_external_set_addr_input_buffer(buf0.physicalAddr);
mlir_aie_external_set_addr_output_buffer(buf1.physicalAddr);
#else
mlir_aie_external_set_addr_input_buffer((u64)ddr_ptr_in);
mlir_aie_external_set_addr_output_buffer((u64)ddr_ptr_out);
#endif
mlir_aie_configure_shimdma_70(_xaie);

mlir_aie_clear_tile_memory(_xaie, 7, 3);
Expand Down Expand Up @@ -151,31 +141,23 @@ int main(int argc, char *argv[]) {
shimdma_stat_s2mm0);
*/

usleep(sleep_u);
printf("before core start\n");
mlir_aie_print_tile_status(_xaie, 7, 3);

printf("Start cores\n");
mlir_aie_start_cores(_xaie);

usleep(sleep_u);
printf("after core start\n");
mlir_aie_print_tile_status(_xaie, 7, 3);
mlir_aie_print_shimdma_status(_xaie, 7, 0);

printf("Release lock for accessing DDR.\n");
mlir_aie_release_input_lock_read(_xaie, 1, 0);

usleep(sleep_u);

if (mlir_aie_acquire_output_lock_read(_xaie, -1, 0)) {
errors++;
}

printf("after lock release\n");
mlir_aie_print_tile_status(_xaie, 7, 3);
mlir_aie_print_shimdma_status(_xaie, 7, 0);

mlir_aie_check("After", mlir_aie_read_buffer_a_ping(_xaie, 3), 4, errors);
mlir_aie_check("After", mlir_aie_read_buffer_a_pong(_xaie, 3), 256 + 4,
errors);
Expand Down
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