Update trace wrappers and add trace test to section-4b (#1733)

Co-authored-by: Jeff Fifield <[email protected]>

programming_guide/section-4/section-4b/Makefile

@@ -57,11 +57,11 @@ run_py: build/final.xclbin
 
 trace: ${targetname}.exe build/trace.xclbin
 	${powershell} ./$< -x build/trace.xclbin -i build/insts.txt -k MLIR_AIE -t ${trace_size}
-	../../../programming_examples/utils/parse_trace.py --filename trace.txt --mlir build/aie_trace.mlir --colshift 1 > trace_4b.json
+	${srcdir}/../../../programming_examples/utils/parse_trace.py --filename trace.txt --mlir build/aie_trace.mlir --colshift 1 > trace_4b.json
 
-trace_py: build/final.xclbin
+trace_py: build/trace.xclbin
 	${powershell} python3 ${srcdir}/test.py -x build/trace.xclbin -i build/insts.txt -k MLIR_AIE -t ${trace_size}
-	../../../programming_examples/utils/parse_trace.py --filename trace.txt --mlir build/aie_trace.mlir --colshift 1 > trace_4b.json
+	${srcdir}/../../../programming_examples/utils/parse_trace.py --filename trace.txt --mlir build/aie_trace.mlir --colshift 1 > trace_4b.json
 
 clean_trace:
 	rm -rf tmpTrace trace.txt trace*json

programming_guide/section-4/section-4b/run_makefile.lit

@@ -7,4 +7,6 @@
  // RUN: make -f %S/Makefile 
  // RUN: %run_on_npu make -f %S/Makefile run | FileCheck %s
  // RUN: %run_on_npu make -f %S/Makefile run_py | FileCheck %s
- // CHECK: PASS!
+ // RUN: make -f %S/Makefile clean
+ // RUN: %run_on_npu make -f %S/Makefile trace_py | FileCheck %s
+ // CHECK: PASS!

python/utils/trace.py

@@ -160,33 +160,23 @@ def pack4bytes(b3, b2, b1, b0):
 # Event numbers should be less than 128.
 # Big assumption: The bd_id and channel are unused.  If they are used by something else, then
 # everything will probably break.
-def configure_simple_tracing_aie2(
+
+
+def configure_coretile_tracing_aie2(
     tile,
-    shim,
-    channel=1,
-    bd_id=13,
-    ddr_id=2,
-    size=8192,
-    offset=0,
     start=CoreEvent.TRUE,
     stop=CoreEvent.NONE,
     events=[
-        CoreEvent.INSTR_EVENT_1,
         CoreEvent.INSTR_EVENT_0,
+        CoreEvent.INSTR_EVENT_1,
         CoreEvent.INSTR_VECTOR,
-        CoreEvent.INSTR_LOCK_RELEASE_REQ,
-        CoreEvent.INSTR_LOCK_ACQUIRE_REQ,
-        CoreEvent.LOCK_STALL,
         PortEvent(CoreEvent.PORT_RUNNING_0, 1, True),  # master(1)
         PortEvent(CoreEvent.PORT_RUNNING_1, 1, False),  # slave(1)
+        CoreEvent.INSTR_LOCK_ACQUIRE_REQ,
+        CoreEvent.INSTR_LOCK_RELEASE_REQ,
+        CoreEvent.LOCK_STALL,
     ],
 ):
-    dev = shim.parent.attributes["device"]
-    tm = get_target_model(dev)
-
-    # Shim has to be a shim tile
-    assert tm.is_shim_noc_tile(shim.col, shim.row)
-
     # For backwards compatibility, allow integers for start/stop events
     if isinstance(start, int):
         start = CoreEvent(start)
@@ -200,11 +190,16 @@ def configure_simple_tracing_aie2(
         )
     events = (events + [CoreEvent.NONE] * 8)[:8]
 
+    # Reorder events so they match the event order for display
+    ordered_events = [events[p] for p in [3, 2, 1, 0, 7, 6, 5, 4]]
+
     # Assure all selected events are valid
-    events = [e if isinstance(e, GenericEvent) else GenericEvent(e) for e in events]
+    ordered_events = [
+        e if isinstance(e, GenericEvent) else GenericEvent(e) for e in ordered_events
+    ]
 
     # Require ports to be specifically given for port events.
-    for event in events:
+    for event in ordered_events:
         if event.code in PortEventCodes and not isinstance(event, PortEvent):
             raise RuntimeError(
                 f"Tracing: {event.code.name} is a PortEvent and requires a port to be specified alongside it. \n"
@@ -242,20 +237,20 @@ def configure_simple_tracing_aie2(
         column=int(tile.col),
         row=int(tile.row),
         address=0x340E0,
-        value=pack4bytes(*(e.code.value for e in events[0:4])),
+        value=pack4bytes(*(e.code.value for e in ordered_events[0:4])),
     )
     # 0x340E4: Trace Event Group 2  (Which events to trace)
     #          0xAABBCCDD    AA, BB, CC, DD <- four event slots
     npu_write32(
         column=int(tile.col),
         row=int(tile.row),
         address=0x340E4,
-        value=pack4bytes(*(e.code.value for e in events[4:8])),
+        value=pack4bytes(*(e.code.value for e in ordered_events[4:8])),
     )
 
     # Event specific register writes
     all_reg_writes = {}
-    for e in events:
+    for e in ordered_events:
         reg_writes = e.get_register_writes()
         for addr, value in reg_writes.items():
             if addr in all_reg_writes:
@@ -265,6 +260,32 @@ def configure_simple_tracing_aie2(
     for addr, value in all_reg_writes.items():
         npu_write32(column=int(tile.col), row=int(tile.row), address=addr, value=value)
 
+
+def configure_broadcast_core_aie2(tile, num, event):
+    addr = 0x34010 + num * 4
+    npu_write32(
+        column=int(tile.col),
+        row=int(tile.row),
+        address=addr,
+        value=event,
+    )
+
+
+def configure_shimtile_tracing_aie2(
+    shim,
+    channel=1,
+    bd_id=13,
+    ddr_id=2,
+    size=8192,
+    offset=0,
+):
+
+    dev = shim.parent.attributes["device"]
+    tm = get_target_model(dev)
+
+    # Shim has to be a shim tile
+    assert tm.is_shim_noc_tile(shim.col, shim.row)
+
     # Configure a buffer descriptor to write tracing information that has been routed into this shim tile
     # out to host DDR memory
     npu_writebd(
@@ -303,3 +324,28 @@ def configure_simple_tracing_aie2(
         address=0x1D204 if channel == 0 else 0x1D20C,
         value=bd_id,
     )
+
+
+def configure_simple_tracing_aie2(
+    tile,
+    shim,
+    channel=1,
+    bd_id=13,
+    ddr_id=2,
+    size=8192,
+    offset=0,
+    start=CoreEvent.TRUE,
+    stop=CoreEvent.NONE,
+    events=[
+        CoreEvent.INSTR_EVENT_0,
+        CoreEvent.INSTR_EVENT_1,
+        CoreEvent.INSTR_VECTOR,
+        PortEvent(CoreEvent.PORT_RUNNING_0, 1, True),  # master(1)
+        PortEvent(CoreEvent.PORT_RUNNING_1, 1, False),  # slave(1)
+        CoreEvent.INSTR_LOCK_ACQUIRE_REQ,
+        CoreEvent.INSTR_LOCK_RELEASE_REQ,
+        CoreEvent.LOCK_STALL,
+    ],
+):
+    configure_coretile_tracing_aie2(tile, start, stop, events)
+    configure_shimtile_tracing_aie2(shim, channel, bd_id, ddr_id, size, offset)

test/python/trace_utils.py

@@ -95,14 +95,14 @@ def sequence(inTensor, outTensor, notUsed):
                         start=0x1,
                         stop=0x0,
                         events=[
-                            PortEvent(0x4B, 1, True),
-                            0x22,
-                            0x21,
                             0x25,
-                            0x2D,
-                            0x2C,
-                            0x1A,
+                            0x21,
+                            0x22,
+                            PortEvent(0x4B, 1, True),
                             PortEvent(0x4F, 1, False),
+                            0x1A,
+                            0x2C,
+                            0x2D,
                         ],
                     )