[aievec][nfc] update mul elem tests and add scalar llvm tests

test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem-llvm-scalar.mlir

@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-generic-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+// XFAIL: *
+
+module {
+  func.func @dut(%arg0: memref<1024xbf16>, %arg1: memref<1024xbf16>, %arg2: memref<1024xbf16>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xbf16>
+    memref.assume_alignment %arg1, 32 : memref<1024xbf16>
+    memref.assume_alignment %arg2, 32 : memref<1024xbf16>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xbf16>
+      %1 = affine.load %arg1[%arg3] : memref<1024xbf16>
+      %2 = arith.mulf %0, %1 : bf16
+      affine.store %2, %arg2[%arg3] : memref<1024xbf16>
+    }
+    return
+  }
+}

test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem-llvm.mlir

@@ -4,7 +4,7 @@
 // REQUIRES: valid_xchess_license
 // REQUIRES: peano
 // RUN: mkdir -p %t/data; cd %t
-// RUN: aie-opt %s %vector-to-llvmir% -o llvmir.mlir
+// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" %vector-to-llvmir% -o llvmir.mlir
 // RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
 // RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
 // RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
@@ -17,12 +17,11 @@ module {
     memref.assume_alignment %arg0, 32 : memref<1024xbf16>
     memref.assume_alignment %arg1, 32 : memref<1024xbf16>
     memref.assume_alignment %arg2, 32 : memref<1024xbf16>
-    %cst = arith.constant 0.000000e+00 : bf16
-    affine.for %arg3 = 0 to 1024 step 16 {
-      %0 = vector.transfer_read %arg0[%arg3], %cst : memref<1024xbf16>, vector<16xbf16>
-      %1 = vector.transfer_read %arg1[%arg3], %cst : memref<1024xbf16>, vector<16xbf16>
-      %2 = arith.mulf %0, %1 : vector<16xbf16>
-      vector.transfer_write %2, %arg2[%arg3] : vector<16xbf16>, memref<1024xbf16>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xbf16>
+      %1 = affine.load %arg1[%arg3] : memref<1024xbf16>
+      %2 = arith.mulf %0, %1 : bf16
+      affine.store %2, %arg2[%arg3] : memref<1024xbf16>
     }
     return
   }

test/unit_tests/aievec_tests/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir

@@ -3,7 +3,7 @@
 
 // REQUIRES: valid_xchess_license
 // RUN: mkdir -p %t/data; cd %t
-// RUN: aie-opt %s --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
+// RUN: aie-opt %s -affine-super-vectorize="virtual-vector-size=16" --convert-vector-to-aievec="aie-target=aieml" -lower-affine | aie-translate -aieml=true --aievec-to-cpp -o dut.cc
 // RUN: xchesscc_wrapper %xchesscc_aie2_args +w work +o work -I%S -I. -c dut.cc -o dut.o
 // RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_CPP +w work +o work -I%S -I. %S/testbench.cc work/dut.o
 // RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
@@ -12,13 +12,12 @@
 
 module {
   func.func @dut(%arg0: memref<1024xbf16>, %arg1: memref<1024xbf16>, %arg2: memref<1024xbf16>) {
-    %cst = arith.constant 0.000000e+00 : bf16
-    affine.for %arg3 = 0 to 1024 step 16 {
-      %0 = vector.transfer_read %arg0[%arg3], %cst : memref<1024xbf16>, vector<16xbf16>
-      %1 = vector.transfer_read %arg1[%arg3], %cst : memref<1024xbf16>, vector<16xbf16>
-      %2 = arith.mulf %0, %1 : vector<16xbf16>
-      vector.transfer_write %2, %arg2[%arg3] : vector<16xbf16>, memref<1024xbf16>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xbf16>
+      %1 = affine.load %arg1[%arg3] : memref<1024xbf16>
+      %2 = arith.mulf %0, %1 : bf16
+      affine.store %2, %arg2[%arg3] : memref<1024xbf16>
     }
     return
   }
-}
+}

test/unit_tests/aievec_tests/i16xi16_mul_elem/i16xi16_mul_elem-llvm-scalar.mlir

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-generic-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi16>, %arg1: memref<1024xi16>, %arg2: memref<1024xi16>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi16>
+    memref.assume_alignment %arg1, 32 : memref<1024xi16>
+    memref.assume_alignment %arg2, 32 : memref<1024xi16>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi16>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi16>
+      %2 = arith.muli %0, %1 : i16
+      affine.store %2, %arg2[%arg3] : memref<1024xi16>
+    }
+    return
+  }
+}

test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem-llvm-scalar.mlir

@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-generic-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi16>, %arg1: memref<1024xi16>, %arg2: memref<1024xi32>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi16>
+    memref.assume_alignment %arg1, 32 : memref<1024xi16>
+    memref.assume_alignment %arg2, 32 : memref<1024xi32>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi16>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi16>
+      %2 = arith.extsi %0 : i16 to i32
+      %3 = arith.extsi %1 : i16 to i32
+      %4 = arith.muli %2, %3 : i32
+      affine.store %4, %arg2[%arg3] : memref<1024xi32>
+    }
+    return
+  }
+}
+

test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem-llvm.mlir

@@ -17,14 +17,13 @@ module {
     memref.assume_alignment %arg0, 32 : memref<1024xi16>
     memref.assume_alignment %arg1, 32 : memref<1024xi16>
     memref.assume_alignment %arg2, 32 : memref<1024xi32>
-    %c0_i16 = arith.constant 0 : i16
-    affine.for %arg3 = 0 to 1024 step 32 {
-      %0 = vector.transfer_read %arg0[%arg3], %c0_i16 : memref<1024xi16>, vector<32xi16>
-      %1 = arith.extsi %0 : vector<32xi16> to vector<32xi32>
-      %2 = vector.transfer_read %arg1[%arg3], %c0_i16 : memref<1024xi16>, vector<32xi16>
-      %3 = arith.extsi %2 : vector<32xi16> to vector<32xi32>
-      %4 = arith.muli %1, %3 : vector<32xi32>
-      vector.transfer_write %4, %arg2[%arg3] : vector<32xi32>, memref<1024xi32>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi16>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi16>
+      %2 = arith.extsi %0 : i16 to i32
+      %3 = arith.extsi %1 : i16 to i32
+      %4 = arith.muli %2, %3 : i32
+      affine.store %4, %arg2[%arg3] : memref<1024xi32>
     }
     return
   }

test/unit_tests/aievec_tests/i16xi16_mul_elem_2/i16xi16_mul_elem.mlir

@@ -12,14 +12,13 @@
 
 module {
   func.func @dut(%arg0: memref<1024xi16>, %arg1: memref<1024xi16>, %arg2: memref<1024xi32>) {
-    %c0_i16 = arith.constant 0 : i16
-    affine.for %arg3 = 0 to 1024 step 32 {
-      %0 = vector.transfer_read %arg0[%arg3], %c0_i16 : memref<1024xi16>, vector<32xi16>
-      %1 = arith.extsi %0 : vector<32xi16> to vector<32xi32>
-      %2 = vector.transfer_read %arg1[%arg3], %c0_i16 : memref<1024xi16>, vector<32xi16>
-      %3 = arith.extsi %2 : vector<32xi16> to vector<32xi32>
-      %4 = arith.muli %1, %3 : vector<32xi32>
-      vector.transfer_write %4, %arg2[%arg3] : vector<32xi32>, memref<1024xi32>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi16>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi16>
+      %2 = arith.extsi %0 : i16 to i32
+      %3 = arith.extsi %1 : i16 to i32
+      %4 = arith.muli %2, %3 : i32
+      affine.store %4, %arg2[%arg3] : memref<1024xi32>
     }
     return
   }

test/unit_tests/aievec_tests/i32xi32_mul_elem/i32xi32_mul_elem-llvm-scalar.mlir

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-generic-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi32>, %arg1: memref<1024xi32>, %arg2: memref<1024xi32>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi32>
+    memref.assume_alignment %arg1, 32 : memref<1024xi32>
+    memref.assume_alignment %arg2, 32 : memref<1024xi32>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi32>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi32>
+      %2 = arith.muli %0, %1 : i32
+      affine.store %2, %arg2[%arg3] : memref<1024xi32>
+    }
+    return
+  }
+}

test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem-llvm-scalar.mlir

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-generic-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi8>, %arg1: memref<1024xi8>, %arg2: memref<1024xi32>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi8>
+    memref.assume_alignment %arg1, 32 : memref<1024xi8>
+    memref.assume_alignment %arg2, 32 : memref<1024xi32>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi8>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi8>
+      %2 = arith.extsi %0 : i8 to i32
+      %3 = arith.extsi %1 : i8 to i32
+      %4 = arith.muli %2, %3 : i32
+      affine.store %4, %arg2[%arg3] : memref<1024xi32>
+    }
+    return
+  }
+}

test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem-llvm.mlir

@@ -17,14 +17,13 @@ module {
     memref.assume_alignment %arg0, 32 : memref<1024xi8>
     memref.assume_alignment %arg1, 32 : memref<1024xi8>
     memref.assume_alignment %arg2, 32 : memref<1024xi32>
-    %c0_i8 = arith.constant 0 : i8
-    affine.for %arg3 = 0 to 1024 step 32 {
-      %0 = vector.transfer_read %arg0[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %1 = arith.extsi %0 : vector<32xi8> to vector<32xi32>
-      %2 = vector.transfer_read %arg1[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %3 = arith.extsi %2 : vector<32xi8> to vector<32xi32>
-      %4 = arith.muli %1, %3 : vector<32xi32>
-      vector.transfer_write %4, %arg2[%arg3] : vector<32xi32>, memref<1024xi32>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi8>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi8>
+      %2 = arith.extsi %0 : i8 to i32
+      %3 = arith.extsi %1 : i8 to i32
+      %4 = arith.muli %2, %3 : i32
+      affine.store %4, %arg2[%arg3] : memref<1024xi32>
     }
     return
   }

test/unit_tests/aievec_tests/i8xi8_mul_elem/i8xi8_mul_elem.mlir

@@ -12,14 +12,13 @@
 
 module {
   func.func @dut(%arg0: memref<1024xi8>, %arg1: memref<1024xi8>, %arg2: memref<1024xi32>) {
-    %c0_i8 = arith.constant 0 : i8
-    affine.for %arg3 = 0 to 1024 step 32 {
-      %0 = vector.transfer_read %arg0[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %1 = arith.extsi %0 : vector<32xi8> to vector<32xi32>
-      %2 = vector.transfer_read %arg1[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %3 = arith.extsi %2 : vector<32xi8> to vector<32xi32>
-      %4 = arith.muli %1, %3 : vector<32xi32>
-      vector.transfer_write %4, %arg2[%arg3] : vector<32xi32>, memref<1024xi32>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi8>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi8>
+      %2 = arith.extsi %0 : i8 to i32
+      %3 = arith.extsi %1 : i8 to i32
+      %4 = arith.muli %2, %3 : i32
+      affine.store %4, %arg2[%arg3] : memref<1024xi32>
     }
     return
   }

test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem-llvm-scalar.mlir

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+// Copyright (C) 2023, Advanced Micro Devices, Inc.
+
+// REQUIRES: valid_xchess_license
+// REQUIRES: peano
+// RUN: mkdir -p %t/data; cd %t
+// RUN: aie-opt %s %vector-to-generic-llvmir% -o llvmir.mlir
+// RUN: aie-translate llvmir.mlir %llvmir-to-ll% -o dut.ll
+// RUN: %PEANO_INSTALL_DIR/bin/clang %clang_aie2_args -c dut.ll -o dut.o
+// RUN: xchesscc_wrapper %xchesscc_aie2_args -DTO_LLVM +w work +o work -I%S -I. %S/testbench.cc dut.o
+// RUN: xca_udm_dbg --aiearch aie-ml -qf -T -P %aietools/data/aie_ml/lib/ -t "%S/../profiling.tcl ./work/a.out" >& xca_udm_dbg.stdout
+// RUN: FileCheck --input-file=./xca_udm_dbg.stdout %s
+// CHECK: TEST PASSED
+
+module {
+  func.func @dut(%arg0: memref<1024xi8>, %arg1: memref<1024xi8>, %arg2: memref<1024xi8>) {
+    memref.assume_alignment %arg0, 32 : memref<1024xi8>
+    memref.assume_alignment %arg1, 32 : memref<1024xi8>
+    memref.assume_alignment %arg2, 32 : memref<1024xi8>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi8>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi8>
+      %2 = arith.muli %0, %1 : i8
+      affine.store %2, %arg2[%arg3] : memref<1024xi8>
+    }
+    return
+  }
+}

test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem-llvm.mlir

@@ -17,12 +17,11 @@ module {
     memref.assume_alignment %arg0, 32 : memref<1024xi8>
     memref.assume_alignment %arg1, 32 : memref<1024xi8>
     memref.assume_alignment %arg2, 32 : memref<1024xi8>
-    %c0_i8 = arith.constant 0 : i8
-    affine.for %arg3 = 0 to 1024 step 32 {
-      %0 = vector.transfer_read %arg0[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %1 = vector.transfer_read %arg1[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %2 = arith.muli %0, %1 : vector<32xi8>
-      vector.transfer_write %2, %arg2[%arg3] : vector<32xi8>, memref<1024xi8>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi8>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi8>
+      %2 = arith.muli %0, %1 : i8
+      affine.store %2, %arg2[%arg3] : memref<1024xi8>
     }
     return
   }

test/unit_tests/aievec_tests/i8xi8_mul_elem_2/i8xi8_mul_elem.mlir

@@ -12,13 +12,13 @@
 
 module {
   func.func @dut(%arg0: memref<1024xi8>, %arg1: memref<1024xi8>, %arg2: memref<1024xi8>) {
-    %c0_i8 = arith.constant 0 : i8
-    affine.for %arg3 = 0 to 1024 step 32 {
-      %0 = vector.transfer_read %arg0[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %1 = vector.transfer_read %arg1[%arg3], %c0_i8 : memref<1024xi8>, vector<32xi8>
-      %2 = arith.muli %0, %1 : vector<32xi8>
-      vector.transfer_write %2, %arg2[%arg3] : vector<32xi8>, memref<1024xi8>
+    affine.for %arg3 = 0 to 1024 {
+      %0 = affine.load %arg0[%arg3] : memref<1024xi8>
+      %1 = affine.load %arg1[%arg3] : memref<1024xi8>
+      %2 = arith.muli %0, %1 : i8
+      affine.store %2, %arg2[%arg3] : memref<1024xi8>
     }
     return
   }
 }
+

test/unit_tests/lit.local.cfg

@@ -26,10 +26,12 @@ if "peano" in config.available_features:
     # pipelines for using aie-opt and aie-translate
     vector_to_aievec = '--convert-vector-to-aievec="aie-target=aieml target-backend=llvmir"'
     aievec_to_llvmir = '--convert-aievec-to-llvm -convert-vector-to-llvm -lower-affine -convert-scf-to-cf -canonicalize -cse -convert-math-to-llvm -expand-strided-metadata -finalize-memref-to-llvm -convert-func-to-llvm -convert-index-to-llvm -canonicalize -cse'
+    vector_to_generic_llvmir = '-canonicalize-vector-for-aievec=aie-target=aieml -convert-vector-to-llvm -lower-affine -convert-scf-to-cf -canonicalize -cse -convert-math-to-llvm -expand-strided-metadata -finalize-memref-to-llvm -convert-func-to-llvm -convert-index-to-llvm -canonicalize -cse'
     llvmir_to_ll = '--mlir-to-llvmir'
     config.substitutions.append(('%vector-to-aievec%', vector_to_aievec))
     config.substitutions.append(('%aievec-to-llvmir%', aievec_to_llvmir))
     config.substitutions.append(('%vector-to-llvmir%', vector_to_aievec+' '+aievec_to_llvmir))
+    config.substitutions.append(('%vector-to-generic-llvmir%', vector_to_generic_llvmir))
     config.substitutions.append(('%llvmir-to-ll%', llvmir_to_ll))