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Xilinx · Apr 23, 2024 · 23588ec · 23588ec
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commit 23588ec
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Showing 3 changed files with 9 additions and 9 deletions.
diff --git a/mlir/test/Conversion/AIRRtToNpu/airrt_to_npu.mlir b/mlir/test/Conversion/AIRRtToNpu/airrt_to_npu.mlir
@@ -519,15 +519,15 @@ module {
 
 // Dealing with scenarios where wrap dimension in airrt.dma_memcpy_nd goes beyond the [0, 1023] hardware limit (test case 2).
 
-// CHECK-LABEL: aie.device(ipu)
+// CHECK-LABEL: aie.device(npu)
 // CHECK:  func.func @func10(%[[ARG0:.*]]: memref<2654208xi32>)
-// CHECK:  aiex.ipu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][3, 3, 768, 32][128, 884736, 1152]) {id = 0 : i64, metadata = @airMemcpyId21} : memref<2654208xi32>
-// CHECK:  aiex.ipu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][3, 3, 768, 32][128, 884736, 1152]) {id = 1 : i64, metadata = @airMemcpyId21} : memref<2654208xi32>
-// CHECK:  aiex.ipu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][3, 3, 768, 32][128, 884736, 1152]) {id = 2 : i64, metadata = @airMemcpyId21} : memref<2654208xi32>
+// CHECK:  aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][3, 3, 768, 32][128, 884736, 1152]) {id = 0 : i64, metadata = @airMemcpyId21} : memref<2654208xi32>
+// CHECK:  aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][3, 3, 768, 32][128, 884736, 1152]) {id = 1 : i64, metadata = @airMemcpyId21} : memref<2654208xi32>
+// CHECK:  aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][3, 3, 768, 32][128, 884736, 1152]) {id = 2 : i64, metadata = @airMemcpyId21} : memref<2654208xi32>
 
 #map = affine_map<()[s0] -> (s0 * 64)>
 module {
-  aie.device(ipu) {
+  aie.device(npu) {
     %tile_0_0 = aie.tile(0, 0)
     aie.shim_dma_allocation @airMemcpyId21(MM2S, 0, 2)
     memref.global "public" @airMemcpyId21 : memref<256x64xbf16, 1>

diff --git a/test/xrt/10_gemm_peeling_extern_vec/aie.py b/test/xrt/10_gemm_peeling_extern_vec/aie.py
@@ -176,7 +176,7 @@
 
     pipeline = "builtin.module("+",".join([
         'canonicalize', 'cse',
-        'air-to-aie{row-offset=2 col-offset=0 device=ipu emit-while-loop=true}',
+        'air-to-aie{row-offset=2 col-offset=0 device=npu emit-while-loop=true}',
         'canonicalize',
     ])+')'
     pm = air.passmanager.PassManager.parse(pipeline)
@@ -193,7 +193,7 @@
       'func.func(affine-loop-opt{affine-opt-tile-sizes=4,4})',
       'func.func(air-unroll-outer-affine-loops{depth=2})',
       'affine-expand-index-ops',
-      'airrt-to-ipu',
+      'airrt-to-npu',
       'canonicalize',
     ])+')'
     pm = air.passmanager.PassManager.parse(pipeline)

diff --git a/test/xrt/10_gemm_peeling_extern_vec/run.lit b/test/xrt/10_gemm_peeling_extern_vec/run.lit
@@ -5,6 +5,6 @@
 
 // RUN: xchesscc_wrapper aie2 -I %aietools/include -c %S/mm.cc -o mm.o
 // RUN: %python %S/aie.py
-// RUN: %python aiecc.py --xchesscc --xbridge --no-aiesim --aie-generate-cdo --aie-generate-ipu --no-compile-host --xclbin-name=aie.xclbin --ipu-insts-name=insts.txt aie.mlir
+// RUN: %python aiecc.py --xchesscc --xbridge --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --xclbin-name=aie.xclbin --npu-insts-name=insts.txt aie.mlir
 // RUN: g++-13 %S/test.cpp -o test.exe -std=c++23 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
-// RUN: %run_on_ipu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt
+// RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt