numorous logic_loop error happened.

[ZHAODONG-LYU]

Hi, when i run synthesis using yosys in caravel_user_project's openlane, at step79.6. Executing CHECK pass (checking for obvious problems). ,1-synthesis.logout many errors as
Warning: found logic loop in module user_project_wrapper:
cell $flatten\inst_eFPGA_top.\Inst_BlockRAM_0.$procmux$1035 ($mux)
cell $flatten\inst_eFPGA_top.\Inst_BlockRAM_1.$procmux$1035 ($mux)
cell $flatten\inst_eFPGA_top.\Inst_BlockRAM_2.$procmux$1035 ($mux)
cell $flatten\inst_eFPGA_top.\Inst_BlockRAM_3.$procmux$1035 ($mux)
cell $flatten\inst_eFPGA_top.\Inst_BlockRAM_4.$procmux$1035 ($mux)
cell $flatten\inst_eFPGA_top.\Inst_BlockRAM_5.$procmux$1035 ($mux)
cell $flatten\inst_eFPGA_top.\Inst_eFPGA.\Tile_X0Y10_W_IO.\Inst_W_IO_switch_matrix.\inst_cus_mux41_buf_E2BEG0.$procmux$489 ($pmux)
cell $flatten\inst_eFPGA_top.\Inst_eFPGA.\Tile_X0Y10_W_IO.\Inst_W_IO_switch_matrix.\inst_cus_mux41_buf_E2BEG1.$procmux$489 ($pmux)
cell $flatten\inst_eFPGA_top.\Inst_eFPGA.\Tile_X0Y10_W_IO.\Inst_W_IO_switch_matrix.\inst_cus_mux41_buf_E2BEG2.$procmux$489 ($pmux)
cell $flatten\inst_eFPGA_top.\Inst_eFPGA.\Tile_X0Y10_W_IO.\Inst_W_IO_switch_matrix.\inst_cus_mux41_buf_E2BEG3.$procmux$489 ($pmux)
cell $flatten\inst_eFPGA_top.\Inst_eFPGA.\Tile_X0Y10_W_IO.\Inst_W_IO_switch_matrix.\inst_cus_mux41_buf_E2BEG4.$procmux$489 ($pmux)
cell $flatten\inst_eFPGA_top.\Inst_eFPGA.\Tile_X0Y10_W_IO.\Inst_W_IO_switch_matrix.\inst_cus_mux41_buf_E2BEG5.$procmux$489 ($pmux)
......
numorous errors,which make this log exceed 2G,so that the process closed withTcl_SetObjLength: negative length requested: -2147479804 (integer overflow?)
I think my design shouldnot have such many logic_loop,is there some config I need to fix?may be some cofings to ignore some rules about logic_loop?

[gatecat]

This looks suspiciously like a fabulous eFPGA?

eFPGAs when viewed 'flat' will contain a very large number of possible logic loops because of the possibility of a bitstream that configures the fabric into a loop (this is as valid as any other bitstream from a point of view of synthesising the fabric).

Probably the easiest trick here is to replace the "muxes" that fabulous uses for switch matrices with one or more relevant primitive instantiations (I think past fabulous tapeouts had a custom cell for these but just instantiating a tree of the relevant sky130 mux2/mux4 cells should work too).

Also not directly related to this problem, but I think past fabulous tapeouts hardened the tiles individually with openlane and then combined them together into the eFPGA to improve placement quality, timing predictability and built times.

[ZHAODONG-LYU]

thanks for your reply.
it is indeed a FABulous eFPGA, and the design i run is what you saidhardened the tiles individually with openlane and then combined them together into the eFPGA, but it doesn't work. i will try the trick you mentioned .
i will give feedback and close this question if i got the solution. thank you.

[ZHAODONG-LYU]

i fix it by updating the openlane version and modify the config match the new files fixed_dont_change .