Mmu2 #4
Mmu2 #4
Conversation
Modify the allocation of app sections in accordance with the requirements for ARM MMU: - Each section size must be a multiple of 4KB (Page size) - Each section must be aligned to 4KB boundary Signed-off-by: Kishore S N <[email protected]>
Signed-off-by: Kishore S N <[email protected]>
os/arch/arm/src/armv7-a/arm_mmu.c
Outdated
| } else { | ||
| // Update L2 page table address in L1 page table. | ||
| val = (uint32_t)l2_pgtbl & PMD_PTE_PADDR_MASK; | ||
| val |= MMU_L1_PGTABFLAGS; |
There was a problem hiding this comment.
this looks wrong, it has some flags that are not needed.
#define MMU_L1_PGTABFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PTE_WRITE_THROUGH | \
PMD_PTE_DOM(0))
There was a problem hiding this comment.
Ok. Will look into it. But changing it is not fixing the issue.
| flags = enter_critical_section(); | ||
| lldbg("Write TTBR = 0x%08x\n", tcb->pgtbl); | ||
| cp15_wrttb((uint32_t)tcb->pgtbl); | ||
| cp15_invalidate_tlbs(); |
There was a problem hiding this comment.
static inline void cp15_invalidate_tlbs(void)
{
__asm__ __volatile__
(
"\tdsb\n"
#ifdef CONFIG_ARM_HAVE_MPCORE
"\tmcr p15, 0, r0, c8, c3, 0\n" /* TLBIALLIS */
"\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
#else
We may also need to invalidate the instruction cache.
mcr p15, 0, r0, c7, c1, 0
|
|
||
| // Update the L2 page table entry. | ||
| idx = (start & 0x000ff000) >> 12; | ||
| val = start & PTE_SMALL_PADDR_MASK; |
There was a problem hiding this comment.
If we are filling the addresses from only the start in the page table, it will miss some entries before start and after end. I think it might not be right?? (May cause prefetch abort when fetching the address that does not have an entry in secondary page table?)
There was a problem hiding this comment.
Agreed. I will change it. But it will not affect our current issue.
| if (!(start & SECTION_MASK) && !(size & SECTION_MASK)) { | ||
| // Yes. Update the section entry in the the L1 page table. | ||
| idx = start >> 20; | ||
| val = start & PMD_PTE_PADDR_MASK; |
There was a problem hiding this comment.
Not required at present, but may be needed to change the mask to section instead of PTE
Set the app pages as global (not using asid), correct the flags while setting ttbr0, populate the l2 page table completely. missing items : 1. indexing of l2 page tables might be wrong, curretnly l2_idx is 0 2. with current implementation, heap end is after page tables, need to adjust it properly. Signed-off-by: Abhishek Akkabathula <[email protected]>
|
@kishore-sn please review the new changes. I have verified the booting. |
No description provided.