RISC-CPU

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

Documentation

This project is implemented in VHDL language with ISE simulator software with a particular specifications.

Relevant course for this project could be computer architecture.

These codes here in github, are just the vhdl and wave files.

If you wanna get the complete project codes, built with ISE go here, find the project title and download the full one.

here is a fairly complete documentaion written in Persian and also English languages: document

This project is licensed under the MIT License - see the LICENSE file for details

Name		Name	Last commit message	Last commit date
Latest commit History 18 Commits
CAR.vhd		CAR.vhd
CZN.vhd		CZN.vhd
ControlMemory.vhd		ControlMemory.vhd
Controller.vhd		Controller.vhd
DI.vhd		DI.vhd
DataPath.vhd		DataPath.vhd
IR.vhd		IR.vhd
LICENSE		LICENSE
MDR.vhd		MDR.vhd
MEM.vhd		MEM.vhd
Main.vhd		Main.vhd
MyCPU.pdf		MyCPU.pdf
PC.vhd		PC.vhd
README.md		README.md
ROM1.vhd		ROM1.vhd
ROM2.vhd		ROM2.vhd
RegFile.vhd		RegFile.vhd
_config.yml		_config.yml
adder.vhd		adder.vhd
alu.vhd		alu.vhd
mux.vhd		mux.vhd
mux_2bits.vhd		mux_2bits.vhd
wave1.wcfg		wave1.wcfg