docs: Add redered wavedrom svgs

Add SVG for all previously committed wavedrom diagrams: axi_pwm_gen, axi_ad485x, add_dds, up_interface axi_jesd204_rx, axi_jesd204_tx, axi_ad7616, axi_ad7606x The source code is kept as a comment block. Signed-off-by: Jorge Marques <[email protected]>
analogdevicesinc · Jan 13, 2025 · 267ea02 · 267ea02
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diff --git a/docs/library/axi_ad485x/index.rst b/docs/library/axi_ad485x/index.rst
@@ -235,7 +235,7 @@ all of the 8 channels and lanes enabled.
 
 There are no extra definitions for the LVDS interface compared to the datasheet.
 
-.. wavedrom::
+.. wavedrom
 
   { "signal" : [
     { "name": "cnvs",    "wave": "010.................................."},
@@ -259,10 +259,13 @@ There are no extra definitions for the LVDS interface compared to the datasheet.
     { "name": "data 5",  "wave": "z...............................4....","data":["ch 5"]},
     { "name": "data 6",  "wave": "z...............................4....","data":["ch 6"]},
     { "name": "data 7",  "wave": "z...............................4....","data":["ch 7"]},
-  ],
-  foot: {text: ['tspan', 'all lanesi(8) all channels(8) active']}}
+  ]}
 
-.. wavedrom::
+.. figure:: wavedrom-1.svg
+
+   all lanesi(8) all channels(8) active.
+
+.. wavedrom
 
   { "signal" : [
     { "name": "cnvs",    "wave": "010.......|.................10......."},
@@ -286,8 +289,11 @@ There are no extra definitions for the LVDS interface compared to the datasheet.
     { "name": "data 5",  "wave": "z..........................4.........","data":["ch 5"]},
     { "name": "data 6",  "wave": "z..........................4.........","data":["ch 6"]},
     { "name": "data 7",  "wave": "z..........................4.........","data":["ch 7"]},
-  ],
-  foot: {text: ['tspan', 'all lanesi(8) all channels(8) active']}}
+  ]}
+
+.. figure:: wavedrom-2.svg
+
+   All lanesi(8) all channels(8) active.
 
 Register Map
 --------------------------------------------------------------------------------

diff --git a/docs/library/axi_ad485x/wavedrom-1.svg b/docs/library/axi_ad485x/wavedrom-1.svg
diff --git a/docs/library/axi_ad485x/wavedrom-2.svg b/docs/library/axi_ad485x/wavedrom-2.svg
diff --git a/docs/library/axi_ad7606x/index.rst b/docs/library/axi_ad7606x/index.rst
@@ -135,7 +135,7 @@ operation followed by a write operation.
    :adi:`AD7606C-18` chip can be obtained from the page 12 of the
    :adi:`AD7606C-18 Datasheet <media/en/technical-documentation/data-sheets/ad7606c-18.pdf>`.
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CS_N', wave:'1.0......|......1..'},
@@ -148,13 +148,15 @@ operation followed by a write operation.
    ]
    }
 
+.. image:: wavedrom-1.svg
+
 The following timing diagrams illustrate available ADC read modes using the
 AD7606x family devices.
 
 ADC Read Mode (AD7606B/C-16)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|......01.'},
@@ -166,10 +168,12 @@ ADC Read Mode (AD7606B/C-16)
    ]
    }
 
+.. image:: wavedrom-2.svg
+
 ADC Read Mode (AD7606C-18)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|......01.'},
@@ -181,10 +185,12 @@ ADC Read Mode (AD7606C-18)
    ]
    }
 
+.. image:: wavedrom-3.svg
+
 ADC Read Mode with CRC enabled (AD7606B/C-16)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|......01.'},
@@ -196,11 +202,12 @@ ADC Read Mode with CRC enabled (AD7606B/C-16)
    ]
    }
 
+.. image:: wavedrom-4.svg
 
 ADC Read Mode with CRC enabled (AD7606C-18)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|......01.'},
@@ -212,10 +219,12 @@ ADC Read Mode with CRC enabled (AD7606C-18)
    ]
    }
 
+.. image:: wavedrom-5.svg
+
 ADC Read Mode with Status enabled (AD7606B/C-16)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|......01.'},
@@ -228,10 +237,12 @@ ADC Read Mode with Status enabled (AD7606B/C-16)
    ]
    }
 
+.. image:: wavedrom-6.svg
+
 ADC Read Mode with Status enabled (AD7606C-18)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|......01.'},
@@ -258,10 +269,12 @@ ADC Read Mode with Status enabled (AD7606C-18)
    ]
    }
 
+.. image:: wavedrom-7.svg
+
 ADC Read Mode with Status and CRC enabled (AD7606B/C-16)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|..........01.'},
@@ -274,10 +287,12 @@ ADC Read Mode with Status and CRC enabled (AD7606B/C-16)
    ]
    }
 
+.. image:: wavedrom-8.svg
+
 ADC Read Mode with Status and CRC enabled (AD7606C-18)
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'CNVST_N', wave: '1..01...........|..........01.'},
@@ -304,6 +319,8 @@ ADC Read Mode with Status and CRC enabled (AD7606C-18)
    ]
    }
 
+.. image:: wavedrom-9.svg
+
 Software Support
 -------------------------------------------------------------------------------
 

diff --git a/docs/library/axi_ad7606x/wavedrom-1.svg b/docs/library/axi_ad7606x/wavedrom-1.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-2.svg b/docs/library/axi_ad7606x/wavedrom-2.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-3.svg b/docs/library/axi_ad7606x/wavedrom-3.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-4.svg b/docs/library/axi_ad7606x/wavedrom-4.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-5.svg b/docs/library/axi_ad7606x/wavedrom-5.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-6.svg b/docs/library/axi_ad7606x/wavedrom-6.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-7.svg b/docs/library/axi_ad7606x/wavedrom-7.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-8.svg b/docs/library/axi_ad7606x/wavedrom-8.svg
diff --git a/docs/library/axi_ad7606x/wavedrom-9.svg b/docs/library/axi_ad7606x/wavedrom-9.svg
diff --git a/docs/library/axi_ad7616/index.rst b/docs/library/axi_ad7616/index.rst
@@ -112,7 +112,7 @@ signal, that is available in the *up_adc_common* module, controls burst_length.
 
 Software Parallel Mode Channel Conversion Setting
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. wavedrom::
+.. wavedrom
 
    {signal: [
      {name: 'RESET_N', wave:'101................'},
@@ -122,37 +122,38 @@ Software Parallel Mode Channel Conversion Setting
      {name: 'WR_N', wave:'1.....01..............01..............', "period" :0.5},
      {name: 'RD_N', wave:'1.................0101................', "period" :0.5},
      {name: 'DB[0:15]', wave:'z.....=.z.........=.=.=.z.........|.....', data: ['CHx',"A0","B0","CHy"], "period" :0.45}
-   ],
-   foot: {text:
-  ['tspan', 'CHx CONVERSION START']
-      }
-   }
+   ]}
+
+.. figure:: wavedrom-1.svg
+
+   CHx CONVERSION START
 
 Parallel Read Timing Diagram
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. wavedrom::
+.. wavedrom
 
-    {signal: [
+   {signal: [
      {name: 'CNVST', wave:'010..........10....'},
      {name: 'BUSY', wave:'0..1......0................1......0...', "period" :0.5},
      {name: 'CS_N', wave:'1..........0..1..0..1..............0..', "period" :0.5},
      {name: 'RD_N', wave:'1......................01........01................................01.', "period" :0.25},
      {name: 'DB[0:15]', wave:'z.....=.z=.z.......', data: ['CONVA',"CONVB","B0","CHy"], "period" :1,"phase":-0.1}
-   ]
- }
+   ]}
+
+.. image:: wavedrom-2.svg
 
 Parallel Write Timing Diagram
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-.. wavedrom::
+.. wavedrom
 
-     {signal: [
+   {signal: [
      {name: 'CNVST', wave:'0..........................1..0', "period" :0.5},
      {name: 'CS_N', wave:'1......0.....1.....0.....1.....', "period" :0.5},
      {name: 'WR_N', wave:'1......0...1.......0...1......', "period" :0.5,"phase":-0.5},
      {name: 'DB[0:15]', wave:'z..=.z.=.z.', data: ['WRITE REG 1',"WRITE REG 2","B0","CHy"], "period" :1.3,"phase":0.7}
-   ]
- }
+   ]}
 
+.. image:: wavedrom-3.svg
 
 Software Support
 --------------------------------------------------------------------------------

diff --git a/docs/library/axi_ad7616/wavedrom-1.svg b/docs/library/axi_ad7616/wavedrom-1.svg
diff --git a/docs/library/axi_ad7616/wavedrom-2.svg b/docs/library/axi_ad7616/wavedrom-2.svg
diff --git a/docs/library/axi_ad7616/wavedrom-3.svg b/docs/library/axi_ad7616/wavedrom-3.svg
diff --git a/docs/library/axi_pwm_gen/index.rst b/docs/library/axi_pwm_gen/index.rst
@@ -173,7 +173,7 @@ Timing Diagrams and examples
 The timing diagram below, shows the ``load_config`` functionality with
 force align and start at sync disabled.
 
-.. wavedrom::
+.. wavedrom
 
   { "signal" : [
     { "name": "clk", "wave": "P................................"},
@@ -191,10 +191,12 @@ force align and start at sync disabled.
     { "name": "pwm 1", "wave": "l....h..l......................h."},
   ]}
 
+.. image:: wavedrom-load_config.svg
+
 The timing diagram below, shows the ``load_config`` functionality with
 force align disabled and start at sync enabled.
 
-.. wavedrom::
+.. wavedrom
 
   { "signal" : [
     { "name": "clk", "wave": "P.............................."},
@@ -212,10 +214,12 @@ force align disabled and start at sync enabled.
     { "name": "pwm 1", "wave": "l....h..l............h....l...."},
   ]}
 
+.. image:: wavedrom-load_config-start_at_sync.svg
+
 The timing diagram below, shows the ``load_config`` functionality with
 force align and start at sync enabled.
 
-.. wavedrom::
+.. wavedrom
 
   { "signal" : [
     { "name": "clk", "wave": "P.............................."},
@@ -233,9 +237,11 @@ force align and start at sync enabled.
     { "name": "pwm 1", "wave": "l....h..l....hl...h....l....h.."},
   ]}
 
+.. image:: wavedrom-load_config-force_align-start_at_sync.svg
+
 The below timing diagrams, shows the ``external_sync`` functionality:
 
-.. wavedrom::
+.. wavedrom
 
   { "signal" : [
     { "name": "clk", "wave": "P............................"},
@@ -251,11 +257,13 @@ The below timing diagrams, shows the ``external_sync`` functionality:
     { "name": "pwm 0", "wave": "l......h..l....h..l....h..l.."},
     { "name": "counter 1", "wave": "=..........44444445555555544=","data":["1","2","3","4","5","6","7","8","1","2","3","4","5","6","7","8","1","2"]},
     { "name": "pwm 1", "wave": "l..........h..l....h..l....h."},
-  ],
-  foot: {text: ['tspan', 'External sync, start at sync (default) e.g.'],
-  }}
+  ]}
+
+.. figure:: wavedrom-external_sync-start_at_sync.svg
 
-.. wavedrom::
+   External sync, start at sync (default).
+
+.. wavedrom
 
   { "signal" : [
     { "name": "clk", "wave": "P............................"},
@@ -271,9 +279,11 @@ The below timing diagrams, shows the ``external_sync`` functionality:
     { "name": "pwm 0", "wave": "l.............h..l....h..l..."},
     { "name": "counter 1", "wave": "=..........44444445555555544=","data":["1","2","3","4","5","6","7","8","1","2","3","4","5","6","7","8","1","2"]},
     { "name": "pwm 1", "wave": "l.................h..l....h.."},
-  ],
-  foot: {text: ['tspan', 'External sync without start at sync e.g.'],
-  }}
+  ]}
+
+.. figure:: wavedrom-external_sync.svg
+
+   External sync without start at sync.
 
 Register Map
 --------------------------------------------------------------------------------

diff --git a/docs/library/axi_pwm_gen/wavedrom-external_sync-start_at_sync.svg b/docs/library/axi_pwm_gen/wavedrom-external_sync-start_at_sync.svg
diff --git a/docs/library/axi_pwm_gen/wavedrom-external_sync.svg b/docs/library/axi_pwm_gen/wavedrom-external_sync.svg
diff --git a/docs/library/axi_pwm_gen/wavedrom-load_config-force_align-start_at_sync.svg b/docs/library/axi_pwm_gen/wavedrom-load_config-force_align-start_at_sync.svg
diff --git a/docs/library/axi_pwm_gen/wavedrom-load_config-start_at_sync.svg b/docs/library/axi_pwm_gen/wavedrom-load_config-start_at_sync.svg
diff --git a/docs/library/axi_pwm_gen/wavedrom-load_config.svg b/docs/library/axi_pwm_gen/wavedrom-load_config.svg
diff --git a/docs/library/common/ad_dds/index.rst b/docs/library/common/ad_dds/index.rst
@@ -285,7 +285,7 @@ equal to the CLOCK_RATIO.
 
 .. image:: fw_sync_basics.svg
 
-.. wavedrom::
+.. wavedrom
 
    {
      "signal" : [
@@ -302,12 +302,12 @@ equal to the CLOCK_RATIO.
        { "name": "tone 2 gen2",  "wave": "=.........5=55|5555555","data":["","i2","","i2+","i2+","i2+","..."]},
        { "name": "tone 2 gen3",  "wave": "=..........555|5555555","data":["","i3","i3+","i3+","i3+","..."]},
        { "name": "tone 2",     "wave": "=.......======|5555555","data":["","0","0","0","0","0","...","s0-3","s4-8","s8-C","..."]},
-       ],
-     foot: {
-       text: ['tspan', 'Frequency word sync at CLK_RATIO=4'],
-     }
+       ]
    }
 
+.. figure:: wavedrom.svg
+
+   text: ['tspan', 'Frequency word sync at CLK_RATIO=4'],
 
 In the above diagram example:
 

diff --git a/docs/library/common/ad_dds/wavedrom.svg b/docs/library/common/ad_dds/wavedrom.svg
diff --git a/docs/library/jesd204/axi_jesd204_rx/index.rst b/docs/library/jesd204/axi_jesd204_rx/index.rst
@@ -277,8 +277,7 @@ signal, but not the TREADY flow control signal. The behavior of the interface is
 as if the TREADY signal was always asserted. This means as soon as ``rx_valid``
 is asserted, a continuous stream of user data must be accepted from ``rx_data``.
 
-.. wavedrom::
-   :align: center
+.. wavedrom
 
    {
       signal: [
@@ -296,6 +295,8 @@ is asserted, a continuous stream of user data must be accepted from ``rx_data``.
          }
    }
 
+.. image:: wavedrom-1.svg
+
 After reset and during link initialization, the ``rx_valid`` signal is
 deasserted. As soon as the User Data Phase is entered, the ``rx_valid`` will be
 asserted to indicate that the peripheral is now providing the processed data
@@ -525,10 +526,7 @@ local-multiblock-clock (LEMC). A setting of 0 indicates that the release
 opportunity is aligned to the LMFC/LEMC edge. A setting of X indicates that it
 trails the LMFC/LEMC edge by X octets.
 
-.. wavedrom::
-   :scale: 100%
-   :align: center
-
+.. wavedrom
    {
       signal: [
          { name: "device_clk", wave: 'P.........' },
@@ -538,6 +536,8 @@ trails the LMFC/LEMC edge by X octets.
       edge: ['a~>b BUFFER DELAY/4']
    }
 
+.. image:: wavedrom-2.svg
+
 The ``BUFFER_DELAY`` field must be set to a multiple of 4. Writing a value that
 is not a multiple of 4 will be rounded down to the next multiple of 4. For
 correct operation, the ``BUFFER_DELAY`` field must also be set to a value

diff --git a/docs/library/jesd204/axi_jesd204_rx/wavedrom-1.svg b/docs/library/jesd204/axi_jesd204_rx/wavedrom-1.svg
diff --git a/docs/library/jesd204/axi_jesd204_rx/wavedrom-2.svg b/docs/library/jesd204/axi_jesd204_rx/wavedrom-2.svg