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library: intel: adi_jesd204: adi_jesd204_hw: Fix sip_tile string #1540

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merged 1 commit into from
Dec 12, 2024
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library: intel: adi_jesd204: adi_jesd204_hw: Fix sip_tile string #1540

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9 changes: 5 additions & 4 deletions library/intel/adi_jesd204/adi_jesd204_hw.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -345,8 +345,9 @@ proc jesd204_compose {} {
set data_path_width [get_parameter_value "DATA_PATH_WIDTH"]
set link_mode [get_parameter_value "LINK_MODE"]

set sip_tile [quartus::device::get_part_info -sip_tile $device]

set sip_tile_info [quartus::device::get_part_info -sip_tile $device]
regexp -nocase {([a-z])\-tile} $sip_tile_info -> sip_tile
set sip_tile [string toupper $sip_tile]

if {$link_mode == 1} {
# jesd204b
Expand Down Expand Up @@ -442,7 +443,7 @@ proc jesd204_compose {} {
add_connection sys_clock.clk_reset link_pll_reset_control.reset
add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown

} elseif {$device_family == "Stratix 10" && $sip_tile == "{H-Tile}"} {
} elseif {$device_family == "Stratix 10" && $sip_tile == "H"} {

send_message info "Instantiate a fpll_s10_htile for link_pll."
add_instance link_pll altera_xcvr_fpll_s10_htile
Expand All @@ -462,7 +463,7 @@ proc jesd204_compose {} {
set outclk_name "outclk_div1"
add_connection link_pll.$outclk_name link_clock.in_clk

} elseif {$device_family == "Stratix 10" && $sip_tile == "E-Tile"} {
} elseif {$device_family == "Stratix 10" && $sip_tile == "E"} {

## No fPLL here, PLL embedded in Native PHY

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