riscv-dv: Use VeeR cpu type for Renode sim

Signed-off-by: Mateusz Karlic <[email protected]>
antmicro · Aug 29, 2024 · 9e778d2 · 9e778d2
1 parent 2e2e1a0
commit 9e778d2
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Showing 5 changed files with 39 additions and 9 deletions.
diff --git a/third_party/riscv-dv b/third_party/riscv-dv
diff --git a/tools/renode/veer.resc b/tools/renode/veer.resc
@@ -7,7 +7,8 @@ $bin?=$ORIGIN/csr_access.elf
 using sysbus
 mach create $name
 
-machine LoadPlatformDescription $ORIGIN/veer.repl
+$platform?=$ORIGIN/veer.repl
+machine LoadPlatformDescription $platform
 
 macro reset
 """

diff --git a/tools/renode/veer.robot b/tools/renode/veer.robot
@@ -25,6 +25,8 @@ Check CSR Access
 
 *** Test Cases ***
 Should Have All CSRs
+    # We are testing SMEPMP registers here, so make sure the extension is active (mseccfg, mseccfgh)
+    Execute Command                 $platform=@${CURDIR}/veer_smepmp.repl
     Prepare Machine                 ${CURDIR}/csr_access.elf
 
     Wait For Line On Uart           ${EMPTY}
@@ -222,7 +224,7 @@ Should Have Correct MStatus
     Wait For Line On Uart           ok.
     Wait For Line On Uart           S mode:
     Wait For Line On Uart           0x800
-    Wait For Line On Uart           0x0
+    Wait For Line On Uart           0x1800
     Wait For Line On Uart           not supported.
     Wait For Line On Uart           U mode:
     Wait For Line On Uart           0x0
@@ -238,7 +240,7 @@ Should Have Correct MStatus
 
     Wait For Line On Uart           Finished: PASSED  matchNextLine=false
 
-Should Have Correcr MISA
+Should Have Correct MISA
     Prepare Machine                 ${CURDIR}/csr_misa.elf
 
     Wait For Line On Uart           misa = 0x40101104 vs. 0x40101104

diff --git a/tools/renode/veer_smepmp.repl b/tools/renode/veer_smepmp.repl
@@ -0,0 +1,12 @@
+mem: Memory.MappedMemory @sysbus 0x80000000
+    size: 0x10000000
+
+htif_mem: Memory.MappedMemory @sysbus 0xD0580000
+    size: 0x1000
+
+cpu: CPU.VeeR_EL2 @ sysbus
+    cpuType: "rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs_Smepmp"
+    hartId: 0
+
+dhry_mem: Memory.MappedMemory @sysbus 0xF0040000
+    size: 0x10000
diff --git a/tools/riscv-dv/Makefile b/tools/riscv-dv/Makefile
@@ -64,6 +64,23 @@ ifeq ("$(.SHELLSTATUS)", "0")
     endif
 endif
 
+ISA_STRING = rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs
+# If compiled with U-mode we implicitly also compile with Smepmp in these tests
+ifeq ($(findstring u, $(RISCV_DV_PRIV)), u)
+	ISA_STRING := "${ISA_STRING}"_smepmp
+endif
+
+RISCV_DV_SIM_ARGS= \
+    --priv m${RISCV_DV_PRIV}
+
+# Append Renode-specific options
+ifeq ("$(RISCV_DV_ISS)", "renode")
+    ISS_OPTS += --cpu-type='VeeR_EL2'
+    ISS_OPTS += --additional-cpu-parameters=''
+    RISCV_DV_SIM_ARGS += \
+        --iss_opts=" ${ISS_OPTS} "
+endif
+
 # riscv-dv args
 RISCV_DV_ARGS = \
     --simulator $(RISCV_DV_SIM) \
@@ -73,16 +90,13 @@ RISCV_DV_ARGS = \
     --start_seed $(RISCV_DV_SEED) \
     --iterations $(RISCV_DV_ITER) \
     --batch_size $(RISCV_DV_BATCH) \
-    --isa rv32imc_zicsr_zifencei_zba_zbb_zbc_zbs \
+    --isa ${ISA_STRING} \
     --mabi ilp32 \
     --priv u \
     --custom_target $(PWD) \
     --testlist $(PWD)/testlist.yaml \
     -v -o $(TEST_DIR)
 
-RISCV_DV_SIM_ARGS= \
-    --priv "$(RISCV_DV_PRIV)"
-
 MAKEFILE  = $(abspath $(MAKEFILE_LIST))
 
 all:
@@ -118,11 +132,12 @@ $(TEST_DIR)/generate.log: | $(TEST_DIR)
 	@touch $@
 
 # Code patching & compilation
+# remove _smepmp from ISA string, as it's not recognized by GCC
 $(TEST_DIR)/compile.log: $(TEST_DIR)
 	# Patch the code
 	find $(TEST_DIR)/asm_test -name "*.S" -exec python3 code_fixup.py -i {} -o {} \;
 	# Compile, simulate
-	PYTHONPATH=$(RISCV_DV_PATH)/pygen python3 $(RISCV_DV_PATH)/run.py $(RISCV_DV_ARGS) \
+	PYTHONPATH=$(RISCV_DV_PATH)/pygen python3 $(RISCV_DV_PATH)/run.py $(subst _smepmp,,$(RISCV_DV_ARGS)) \
     --steps gcc_compile 2>&1 | tee $@
 
 # ISS simulation
+1 −0		run.py
+2 −0		scripts/instr_trace_compare.py
+36 −2		scripts/renode_wrapper.py
+2 −2		yaml/iss.yaml