Updating dma with new packet format

aolofsson · May 15, 2016 · f9613d8 · f9613d8
1 parent d0b5fcd
commit f9613d8
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Showing 4 changed files with 48 additions and 60 deletions.
diff --git a/src/edma/hdl/edma.v b/src/edma/hdl/edma.v
@@ -4,57 +4,38 @@
 //# Author:   Andreas Olofsson                                                #
 //# License:  MIT (see below)                                                 # 
 //#############################################################################
-module edma (/*AUTOARG*/
-   // Outputs
-   irq, wait_out, access_out, packet_out, reg_wait_out,
-   reg_access_out, reg_packet_out,
-   // Inputs
-   vdd, vss, clk, nreset, access_in, packet_in, wait_in,
-   reg_access_in, reg_packet_in, reg_wait_in
-   );
-
-   //#####################################################################
-   //# INTERFACE
-   //#####################################################################
-
-   //parameters
-   parameter  AW  = 32;           // address width
-   localparam PW  = 2*AW+40;      // emesh packet width
-
-   // power
-   input           vdd;           // supply
-   input           vss;           // common ground
-
-   // reset, clk, config
-   input           clk;           // main core clock   
-   input 	   nreset;        // async active low reset
-   output 	   irq;           // interrupt output
-
-   // datapath interface
-   input 	   access_in;     // streaming input access
-   input [PW-1:0]  packet_in;     // streaming input data 
-   output 	   wait_out;      // pushback
-
-   output 	   access_out;    // output access (master/slave)
-   output [PW-1:0] packet_out;    // output packet (with address)
-   input 	   wait_in;       // pushback
-
-   // config/fetch interface
-   input 	   reg_access_in; // config register access
-   input [PW-1:0]  reg_packet_in; // config register packet
-   output          reg_wait_out;  // pushback by register read
-
-   output 	   reg_access_out;// config readback
-   output [PW-1:0] reg_packet_out;// config reacback packet
-   input 	   reg_wait_in;   // pushback for readback
+module edma #( parameter AW  = 32,  // address width
+	       parameter PW  = 104 // packet width
+	       ) 
+   (
+    // power
+    input 	    vdd, // supply
+    input 	    vss, // common ground
+    // reset, clk, config
+    input 	    clk, // main core clock   
+    input 	    nreset, // async active low reset
+    output 	    irq, // interrupt output
+    // datapath interface
+    input 	    access_in, // streaming input access
+    input [PW-1:0]  packet_in, // streaming input data 
+    output 	    wait_out, // pushback
+    output 	    access_out, // output access (master/slave)
+    output [PW-1:0] packet_out, // output packet (with address)
+    input 	    wait_in, // pushback
+    // config/fetch interface
+    input 	    reg_access_in, // config register access
+    input [PW-1:0]  reg_packet_in, // config register packet
+    output 	    reg_wait_out, // pushback by register read
+    output 	    reg_access_out,// config readback
+    output [PW-1:0] reg_packet_out,// config reacback packet
+    input 	    reg_wait_in    // pushback for readback
+    );
 
-   //#####################################################################
-   //# BODY
-   //#####################################################################
-
+   //###############
+   //# LOCAL WIRES
+   //###############
    /*AUTOOUTPUT*/
-   /*AUTOINPUT*/
-
+   /*AUTOINPUT*/   
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire			chainmode;		// From edma_regs of edma_regs.v
@@ -84,7 +65,8 @@ module edma (/*AUTOARG*/
    //# DATAPATH
    //##########################
 
-   edma_dp #(.AW(AW))
+   edma_dp #(.AW(AW),
+	     .PW(PW))
    edma_dp(/*AUTOINST*/
 	   // Outputs
 	   .count			(count[31:0]),
@@ -112,7 +94,8 @@ module edma (/*AUTOARG*/
    //# CONFIG REGISTERS
    //##########################
 
-   edma_regs #(.AW(AW))
+   edma_regs #(.AW(AW),
+	       .PW(PW))
    edma_regs (/*AUTOINST*/
 	      // Outputs
 	      .reg_wait_out		(reg_wait_out),
@@ -149,7 +132,8 @@ module edma (/*AUTOARG*/
    //# STATE MACHINE
    //##########################
 
-   edma_ctrl #(.AW(AW))
+   edma_ctrl #(.AW(AW),
+	       .PW(PW))
    edma_ctrl (/*AUTOINST*/
 	      // Outputs
 	      .fetch_access		(fetch_access),

diff --git a/src/edma/hdl/edma_ctrl.v b/src/edma/hdl/edma_ctrl.v
@@ -16,7 +16,7 @@ module edma_ctrl (/*AUTOARG*/
    );
 
    parameter  AW  = 32;            // address width
-   localparam PW  = 2*AW+40;      // fetch packet width
+   parameter  PW  = 2*AW+40;      // fetch packet width
    parameter  ID  = 4'b0000;      // group id for DMA regs [10:8]
 
    // clk, reset, config
@@ -170,7 +170,8 @@ module edma_ctrl (/*AUTOARG*/
 				 2'b0};            //1-0
 
    // constructing fetch packet
-   emesh2packet #(.AW(AW))
+   emesh2packet #(.AW(AW),
+		  .PW(PW))
    e2p (//outputs
 	.packet_out	(fetch_packet[PW-1:0]),
 	//inputs        

diff --git a/src/edma/hdl/edma_dp.v b/src/edma/hdl/edma_dp.v
@@ -13,8 +13,8 @@ module edma_dp (/*AUTOARG*/
    packet_in, wait_in
    );
 
-   parameter AW   = 8;            // divider counter width
-   localparam PW  = 2*AW+40;      // emesh packet width
+   parameter  AW   = 8;            // divider counter width
+   parameter  PW  = 2*AW+40;      // emesh packet width
 
    // clk, reset, config
    input           clk;           // main clock
@@ -99,7 +99,8 @@ module edma_dp (/*AUTOARG*/
    //################################ 
 
    // parsing input packet
-   packet2emesh #(.AW(AW))
+   packet2emesh #(.AW(AW),
+		  .PW(PW))
    p2e (/*AUTOINST*/
 	// Outputs
 	.write_in			(write_in),
@@ -121,7 +122,8 @@ module edma_dp (/*AUTOARG*/
    assign srcaddr_out[AW-1:0] = master_active ? {(AW){1'b0}}  : srcaddr_in[31:0];
 
    // constructing output packet
-   emesh2packet #(.AW(AW))
+   emesh2packet #(.AW(AW),
+		  .PW(PW))
    e2p (.packet_out			(packet[PW-1:0]),
      /*AUTOINST*/
 	// Inputs

diff --git a/src/edma/hdl/edma_regs.v b/src/edma/hdl/edma_regs.v
@@ -19,7 +19,7 @@ module edma_regs (/*AUTOARG*/
 
    // parameters 
    parameter  AW      = 8;         // address width
-   localparam PW      = 2*AW+40;   // emesh packet width
+   parameter  PW      = 2*AW+40;   // emesh packet width
    parameter  DEF_CFG = 0;         // default config after reset   
 
    // clk, reset
@@ -105,7 +105,8 @@ module edma_regs (/*AUTOARG*/
    //# DECODE
    //################################
 
-   packet2emesh #(.AW(AW))
+   packet2emesh #(.AW(AW),
+		  .PW(PW))
    p2e (.packet_in			(reg_packet_in[PW-1:0]),
 	/*AUTOINST*/
 	// Outputs