Spi cpol0 cpha0 #85
Open
Spi cpol0 cpha0 #85
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Solves issue with master STATUS[0] always high. Signed-off-by: Ola Jeppsson <[email protected]>
Signed-off-by: Ola Jeppsson <[email protected]>
Make sure neither synthesis or simulation can go through with an empty block. Signed-off-by: Ola Jeppsson <[email protected]>
Signed-off-by: Ola Jeppsson <[email protected]>
Stabilizes output in simulation. Signed-off-by: Ola Jeppsson <[email protected]>
Fixes iverilog warning. Signed-off-by: Ola Jeppsson <[email protected]>
In CPOL=0 CPHA=0 (MODE=0) the master outputs M0SI on the falling edge of SCLK, and samples MISO on the rising edge of SCLK. Signed-off-by: Ola Jeppsson <[email protected]>
Signed-off-by: Ola Jeppsson <[email protected]>
CPOL=0 CPHA=0 mode: RX data is sampled on rising edge. TX data is outputted on falling edge. Between the first byte is received and the second byte should start transmitting, we have a half clock cycle so we need to bypass the deserializer for the last MOSI bit and grab it directly from the pin. Signed-off-by: Ola Jeppsson <[email protected]>
Use oh_fifo_cdc for XILINX target. oh_fifo_sync does work in simulation but it does not work when synthesizing in Vivado (see aolofsson#84). This also includes a hack that forces the FIFO depth/width to 32/104 when TARGET is set to "XILINX" (only available FIFO IP atm.). Signed-off-by: Ola Jeppsson <[email protected]>
Should output 0x00fedcba98765432 to master receive FIFO register. Signed-off-by: Ola Jeppsson <[email protected]>
Signed-off-by: Ola Jeppsson <[email protected]>
Fixes iverilog warning. Signed-off-by: Ola Jeppsson <[email protected]>
Allow setting SLEW rate in single-ended mode. Signed-off-by: Ola Jeppsson <[email protected]>
Signed-off-by: Ola Jeppsson <[email protected]>
olajep
force-pushed
the
spi-cpol0-cpha0
branch
2 times, most recently
from
d9b3d85
to
ac65c14
Compare
Estimated values, seems close to HW limits though. TX just barely misses 100 MHz timing. Signed-off-by: Ola Jeppsson <[email protected]>
Signed-off-by: Ola Jeppsson <[email protected]>
Ensure that SS=1 for at least one SCLK clock cycle between transfers. Fixes race condition where the slave misses the end of transfer signal. Signed-off-by: Ola Jeppsson <[email protected]>
olajep
force-pushed
the
spi-cpol0-cpha0
branch
2 times, most recently
from
afdc3ec
to
838c149
Compare
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Makes master/slave MODE=0 (CPOL=0 CPHA=0)
(The master transmitted in CPHA=0 but sampled in CPHA=1, similarly the slave sampled in CPHA=0 but transmitted in CPHA=1)
Works around XILINX issue w/ oh_fifo_sync (see #84)
// Ola