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Adding the configs with heater+IBERT to master (#63)
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* adding rev2 configs with heaters and IBERT

* Delete config/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G directory

* cleaning up heater control code

* fixng typos

* adding the heater fw&ibert for rev2
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@rzouCERN
rzouCERN authored Nov 1, 2024
1 parent c93ba80 commit 7d91c6f
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4 changes: 4 additions & 0 deletions .gitmodules
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path = build-scripts
url = https://gitlab.com/BU-EDF/fw-bits/build-scripts.git
branch = develop
[submodule "configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater"]
path = configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater
url = https://github.com/apollo-lhc/FPGA_heater.git
[submodule "configs/IT-DTC_p1_VU13p-1/it-dtc-fw"]
path = configs/IT-DTC_p1_VU13p-1/it-dtc-fw
url = https://gitlab.com/apollo-lhc/it-dtc/it-dtc-fw.git

1 change: 1 addition & 0 deletions configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/FPGA_heater
Submodule FPGA_heater added at 04e423
32 changes: 32 additions & 0 deletions configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/Generate_svf.tcl
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#this has to be called from inside an open session
source ${apollo_root_path}/configs/${build_name}/settings.tcl

set SVF_TARGET [format "svf_top%06u" [expr {round(1000000 *rand())}]]



#derived from walkthrough https://blog.xjtag.com/2016/07/creating-svf-files-using-xilinx-vivado/
open_hw
if { [string length [get_hw_targets -quiet -regexp .*/${SVF_TARGET}] ] } {
delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]
}
create_hw_target ${SVF_TARGET}
close_hw_target
open_hw_target [get_hw_targets -regexp .*/${SVF_TARGET}]


#1st in chain, no need to add another FPGA to the chain
#create_hw_device -part xcku15p-ffva1760-2-e

#add the virtex to the chain
set DEVICE [create_hw_device -part ${FPGA_part}]
set_property PROGRAM.FILE ${apollo_root_path}/bit/top_${build_name}.bit $DEVICE
set_param xicom.config_chunk_size 0
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]


program_hw_devices -force -svf_file ${apollo_root_path}/bit/top_${build_name}.svf ${DEVICE}

write_cfgmem -force -loadbit "up 0 ${apollo_root_path}/bit/top_${build_name}.bit" -format mcs -size 128 -file "${apollo_root_path}/bit/top_${build_name}.mcs"

delete_hw_target -quiet [get_hw_targets -regexp .*/${SVF_TARGET}]
101 changes: 101 additions & 0 deletions configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/config.yaml
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AXI_CONTROL_SETS:
AXI_MASTER_CTRL:
axi_interconnect: "${::AXI_INTERCONNECT_NAME}"
axi_clk: "${::AXI_MASTER_CLK}"
axi_rstn: "${::AXI_MASTER_RSTN}"
axi_freq: "${::AXI_MASTER_CLK_FREQ}"


AXI_SLAVES:
F1_IO:
TCL_CALL:
command: AXI_PL_DEV_CONNECT
axi_control: "${::AXI_MASTER_CTRL}"
addr:
offset: "0xB1002000"
range: "4K"
remote_slave: "1"
XML: "address_table/modules/CM_IO.xml"
UHAL_BASE: 0x81000000
HDL:
out_name: "IO"
map_template: "axi_generic/template_map_withbram.vhd"
F1_SYS_MGMT:
TCL_CALL:
command: AXI_IP_SYS_MGMT
enable_i2c_pins: 1
axi_control: "${::AXI_MASTER_CTRL}"
addr:
offset: "0xB1001000"
range: "4K"
remote_slave: "1"
XML: "address_table/modules/VIRTEX_SYS_MGMT.xml"
UHAL_BASE: 0x80000000

F1_CM_FW_INFO:
TCL_CALL:
command: AXI_PL_DEV_CONNECT
axi_control: "${::AXI_MASTER_CTRL}"
addr:
offset: "0xB1003000"
range: "4K"
remote_slave: "1"
XML: "address_table/modules/FW_INFO.xml"
UHAL_BASE: 0x82000000
HDL:
out_name: "CM_FW_INFO"
map_template: "axi_generic/template_map.vhd"


F1_IPBUS:
TCL_CALL:
command: AXI_PL_DEV_CONNECT
axi_control: "${::AXI_MASTER_CTRL}"
type: "AXI4"
addr:
offset: "0xB0000000"
range: "16M"
data_width: "64"
remote_slave: "1"
XML: "address_table/modules/IPBUS.xml"
UHAL_BASE: 0x85000000

F1_C2C_INTF:
TCL_CALL:
command: AXI_PL_DEV_CONNECT
axi_control: "${::AXI_MASTER_CTRL}"
addr:
offset: "0xB1010000"
range: "64K"
remote_slave: "1"
XML: "address_table/modules/C2C_INTFS.xml"
UHAL_BASE: 0x86000000
HDL:
out_name: "C2C_INTF"
map_template: "axi_generic/template_map_withbram.vhd"
SUB_SLAVES:
CM1_PB_UART:
TCL_CALL:
command: "AXI_IP_UART"
addr:
offset: "0xB1008000"
range: "4K"
irq_port: "F1_C2CB/axi_c2c_s2m_intr_in"
baud_rate: "115200"
axi_control: "${::AXI_MASTER_CTRL}"
manual_load_dtsi: "1"
remote_slave: "1"
dt_data: "compatible = \"xlnx,axi-uartlite-2.0\", \"xlnx,xps-uartlite-1.00.a\";current-speed = <115200>;device_type = \"serial\";interrupt-names = \"interrupt\";interrupt-parent = <&IRQ0_INTR_CTRL>;interrupts = <4 0>;port-number = <101>;xlnx,baudrate = <0x1c200>;xlnx,data-bits = <0x8>;xlnx,odd-parity = <0x0>;xlnx,s-axi-aclk-freq-hz-d = \"49.9995\";xlnx,use-parity = <0x0>;
"

CORES:
onboardclk:
TCL_CALL:
command: BuildClockWizard
in_clk_type: Differential_clock_capable_pin
in_clk_freq_MHZ: 200
out_clks:
1: 200
2: 50


60 changes: 60 additions & 0 deletions configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/files.tcl
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set bd_path proj

array set bd_files [list {c2cSlave} {configs/${build_name}/createC2CSlaveInterconnect.tcl} \
]

set vhdl_files "\
configs/${build_name}/src/top.vhd \
configs/${build_name}/FPGA_heater/heater.vhd \
configs/${build_name}/FPGA_heater/lut_oscillator.vhd \
configs/${build_name}/src/ibert_ultrascale_gty_l.vhd \
configs/${build_name}/src/ibert_ultrascale_gty_r.vhd \
configs/${build_name}/src/VIRTEX_TCDS_map.vhd \
configs/${build_name}/src/VIRTEX_TCDS_PKG.vhd \
configs/${build_name}/src/TCDS.vhd \
src/misc/DC_data_CDC.vhd \
src/misc/pacd.vhd \
src/misc/types.vhd \
src/misc/capture_CDC.vhd \
src/misc/counter.vhd \
src/misc/counter_CDC.vhd \
regmap_helper/axiReg/axiRegWidthPkg_32.vhd \
regmap_helper/axiReg/axiRegPkg_d64.vhd \
regmap_helper/axiReg/axiRegPkg.vhd \
regmap_helper/axiReg/axiReg.vhd \
regmap_helper/axiReg/bramPortPkg.vhd \
regmap_helper/axiReg/axiRegBlocking.vhd \
src/C2C_INTF/C2C_Intf.vhd \
src/C2C_INTF/CM_phy_lane_control.vhd \
src/RGB_PWM.vhd \
src/LED_PWM.vhd \
src/misc/rate_counter.vhd \
src/CM_FW_info/CM_FW_info.vhd \
${autogen_path}/IO/IO_PKG.vhd \
${autogen_path}/IO/IO_map.vhd \
${autogen_path}/C2C_INTF/C2C_INTF_map.vhd \
${autogen_path}/C2C_INTF/C2C_INTF_PKG.vhd \
${autogen_path}/CM_FW_INFO/CM_FW_INFO_PKG.vhd \
${autogen_path}/CM_FW_INFO/CM_FW_INFO_map.vhd \
src/C2C_INTF/picoblaze/picoblaze/kcpsm6.vhd \
src/C2C_INTF/picoblaze/uart_rx6.vhd \
src/C2C_INTF/picoblaze/uart_tx6.vhd \
src/C2C_INTF/picoblaze/uC.vhd \
src/C2C_INTF/picoblaze/picoblaze/cli.vhd \
"
set xdc_files "\
configs/${build_name}/src/top_pins.xdc \
configs/${build_name}/src/top_timing.xdc \
configs/${build_name}/src/top_heaters.xdc \
configs/${build_name}/src/ibert_ultrascale_gty_l.xdc \
configs/${build_name}/src/ibert_ultrascale_gty_l_clockgroups.xdc \
configs/${build_name}/src/ibert_ultrascale_gty_r.xdc \
configs/${build_name}/src/ibert_ultrascale_gty_r_clockgroups.xdc \
"

set xci_files "\
cores/AXI_BRAM/AXI_BRAM.xci \
cores/DP_BRAM/DP_BRAM.xci \
configs/${build_name}/src/ibert_ultrascale_gty_core_l/ibert_ultrascale_gty_core_l.xci \
configs/${build_name}/src/ibert_ultrascale_gty_core_r/ibert_ultrascale_gty_core_r.xci \
"
19 changes: 19 additions & 0 deletions configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/settings.tcl
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#set the FPGA part number
set FPGA_part xcvu13p-flga2577-1-e

##for c2c
set C2C F1_C2C
set C2C_PHY ${C2C}_PHY
set C2CB F1_C2CB
set C2CB_PHY ${C2CB}_PHY

#create remote device tree entries, 64 bit
global REMOTE_C2C_64
set REMOTE_C2C_64 1


set top top

set outputDir ./

105 changes: 105 additions & 0 deletions configs/Cornell_rev2_p1_VU13p-1-SM_USP_heaters_allQuads25G/src/VIRTEX_TCDS_PKG.vhd
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--This file was auto-generated.
--Modifications might be lost.
library IEEE;
use IEEE.std_logic_1164.all;


package VIRTEX_TCDS_CTRL is
type VIRTEX_TCDS_CLOCKING_MON_t is record
COUNTS_REFCLK0 : std_logic_vector(31 downto 0);
COUNTS_TXOUTCLK : std_logic_vector(31 downto 0);
POWER_GOOD : std_logic;
QPLL0_FBCLKLOST : std_logic;
QPLL0_LOCK : std_logic;
QPLL0_REFCLKLOST : std_logic;
RX_CDR_STABLE : std_logic;
end record VIRTEX_TCDS_CLOCKING_MON_t;

type VIRTEX_TCDS_RESETS_MON_t is record
RX_PMA_RESET_DONE : std_logic;
RX_RESET_DONE : std_logic;
TX_PMA_RESET_DONE : std_logic;
TX_RESET_DONE : std_logic;
end record VIRTEX_TCDS_RESETS_MON_t;

type VIRTEX_TCDS_RESETS_CTRL_t is record
RESET_ALL : std_logic;
RX_DATAPATH : std_logic;
RX_PLL_DATAPATH : std_logic;
TX_DATAPATH : std_logic;
TX_PLL_DATAPATH : std_logic;
end record VIRTEX_TCDS_RESETS_CTRL_t;

type VIRTEX_TCDS_RX_MON_t is record
BAD_CHAR : std_logic_vector( 3 downto 0);
DISP_ERROR : std_logic_vector( 3 downto 0);
PMA_RESET_DONE : std_logic;
end record VIRTEX_TCDS_RX_MON_t;

type VIRTEX_TCDS_RX_CTRL_t is record
PRBS_RESET : std_logic;
PRBS_SEL : std_logic_vector( 3 downto 0);
USER_CLK_READY : std_logic;
end record VIRTEX_TCDS_RX_CTRL_t;

type VIRTEX_TCDS_TX_MON_t is record
PMA_RESET_DONE : std_logic;
PWR_GOOD : std_logic;
end record VIRTEX_TCDS_TX_MON_t;

type VIRTEX_TCDS_TX_CTRL_t is record
INHIBIT : std_logic;
PRBS_FORCE_ERROR : std_logic;
PRBS_SEL : std_logic_vector( 3 downto 0);
USER_CLK_READY : std_logic;
end record VIRTEX_TCDS_TX_CTRL_t;

type VIRTEX_TCDS_EYESCAN_CTRL_t is record
RESET : std_logic;
TRIGGER : std_logic;
end record VIRTEX_TCDS_EYESCAN_CTRL_t;

type VIRTEX_TCDS_DEBUG_MON_t is record
CAPTURE_D : std_logic_vector(31 downto 0);
CAPTURE_K : std_logic_vector( 3 downto 0);
end record VIRTEX_TCDS_DEBUG_MON_t;

type VIRTEX_TCDS_DEBUG_CTRL_t is record
CAPTURE : std_logic;
FIXED_SEND_D : std_logic_vector(31 downto 0);
FIXED_SEND_K : std_logic_vector( 3 downto 0);
MODE : std_logic_vector( 3 downto 0);
end record VIRTEX_TCDS_DEBUG_CTRL_t;

type VIRTEX_TCDS_Heater_MON_t is record
Output : std_logic_vector(31 downto 0);
end record VIRTEX_TCDS_Heater_MON_t;

type VIRTEX_TCDS_Heater_CTRL_t is record
Adjust : std_logic_vector(31 downto 0);
Enable : std_logic;
SelectHeater : std_logic_vector(31 downto 0);
end record VIRTEX_TCDS_Heater_CTRL_t;

type VIRTEX_TCDS_MON_t is record
CLOCKING : VIRTEX_TCDS_CLOCKING_MON_t;
DEBUG : VIRTEX_TCDS_DEBUG_MON_t;
Heater : VIRTEX_TCDS_Heater_MON_t;
RESETS : VIRTEX_TCDS_RESETS_MON_t;
RX : VIRTEX_TCDS_RX_MON_t;
TX : VIRTEX_TCDS_TX_MON_t;
end record VIRTEX_TCDS_MON_t;

type VIRTEX_TCDS_CTRL_t is record
DEBUG : VIRTEX_TCDS_DEBUG_CTRL_t;
EYESCAN : VIRTEX_TCDS_EYESCAN_CTRL_t;
Heater : VIRTEX_TCDS_Heater_CTRL_t;
LOOPBACK : std_logic_vector( 2 downto 0);
RESETS : VIRTEX_TCDS_RESETS_CTRL_t;
RX : VIRTEX_TCDS_RX_CTRL_t;
TX : VIRTEX_TCDS_TX_CTRL_t;
end record VIRTEX_TCDS_CTRL_t;



end package VIRTEX_TCDS_CTRL;
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