Contributors: Bharat Arora 2014B3A70629G Vadaga Ananyo Rao 2014B5A70910G Yeshwanth Reddy Beeram 2015A7PS0031G Sri Harish G 2015A7PS0041G Silpa Soni 2015A7PS0054G Surya Pratap Mehra 2015A7PS0063G

Offset = 2 bits Index = 4 bits Tag = 26 bits

Cache size = 512B

Way prediction size = 4 bits

Control Circuit Design: Silpa Soni (20%)

Cache Design and Implementation: Bharat Arora (20%) and Vadaga Ananyo Rao (20%)

Datapath Design and Implementation: Sri Harish G (20%) and Surya Pratap Mehra (20%)

Our datapath and Cache modules are working independently. Testbenches for their indivitual working have been included. However, the complete integrated circuit is not giving the desired output.