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Issue 91 update publish to happen to real pypi (#92)
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* Update ci.yml to use real pypi

* cocotb fix

* Test pypi

* Fix cocotb warnings

* Change back to using real pypi
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bensampson5 authored Oct 29, 2021
1 parent 5af5b56 commit c723f37
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Showing 13 changed files with 30 additions and 33 deletions.
3 changes: 1 addition & 2 deletions .github/workflows/ci.yml
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Expand Up @@ -127,5 +127,4 @@ jobs:
uses: pypa/gh-action-pypi-publish@release/v1
with:
user: __token__
password: ${{ secrets.PYPI_TEST_API_TOKEN }}
repository_url: https://test.pypi.org/legacy/
password: ${{ secrets.PYPI_API_TOKEN }}
4 changes: 2 additions & 2 deletions Dockerfile.dev
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@@ -1,6 +1,6 @@
ARG BRANCH=main
ARG TAG=main

FROM bensampson5/libsv:${BRANCH}
FROM bensampson5/libsv:${TAG}

ARG DEBIAN_FRONTEND=noninteractive
RUN apt-get update \
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9 changes: 4 additions & 5 deletions README.rst
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Expand Up @@ -19,11 +19,10 @@
Welcome to LibSV! `Click here to go to LibSV’s
documentation <https://libsv.readthedocs.io/en/latest/>`_.

LibSV is a library of open source, parameterized digital logic IP
written in SystemVerilog. While similar libraries may already exist, LibSV
is unique in that it takes advantage of open-source, state-of-the-art
development best practices and tools from across the software and
digital design community, including:
LibSV is an open source, parameterized SystemVerilog digital hardware IP library.
While similar libraries may already exist, LibSV is unique in that it takes advantage
of open-source, state-of-the-art development best practices and tools from across the
software and digital design community, including:

* Trivial installation. `LibSV is hosted on PyPI <https://pypi.org/project/libsv/>`_ and can easily be installed using
`pip <https://pip.pypa.io/en/stable/>`_ or whichever Python package manager of your choice.
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4 changes: 2 additions & 2 deletions docs/source/contributing.rst
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Expand Up @@ -67,14 +67,14 @@ Once you have Docker installed you can build and pull the LibSV Docker image by
-t libsv .
By default, this will pull the LibSV Docker image associated with the ``main`` branch, however you can pull a different branch's
LibSV Docker image by adding the ``BRANCH`` build argument:
LibSV Docker image (or any tagged version) by adding the ``TAG`` build argument:

.. code-block:: bash
docker build --pull -f Dockerfile.dev \
--build-arg UID=$(id -u) \
--build-arg GID=$(id -g) \
--build-arg BRANCH=TYPE_BRANCH_NAME_HERE \
--build-arg TAG=TAG_NAME \
-t libsv .
Then, start a new Docker container using the LibSV image and mount the project folder to the container:
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9 changes: 4 additions & 5 deletions docs/source/index.rst
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Expand Up @@ -8,11 +8,10 @@
Welcome to LibSV's documentation!
=================================

LibSV is a library of open source, parameterized digital logic IP
written in SystemVerilog. While similar libraries may already exist, LibSV
is unique in that it takes advantage of open-source, state-of-the-art
development best practices and tools from across the software and
digital design community, including:
LibSV is an open source, parameterized SystemVerilog digital hardware IP library.
While similar libraries may already exist, LibSV is unique in that it takes advantage
of open-source, state-of-the-art development best practices and tools from across the
software and digital design community, including:

* Trivial installation. `LibSV is hosted on PyPI <https://pypi.org/project/libsv/>`_ and can easily be installed using
`pip <https://pip.pypa.io/en/stable/>`_ or whichever Python package manager of your choice.
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2 changes: 1 addition & 1 deletion pyproject.toml
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Expand Up @@ -8,7 +8,7 @@ license = "MIT"
repository = "https://github.com/bensampson5/libsv"
homepage = "https://libsv.readthedocs.io/en/latest/"
documentation = "https://libsv.readthedocs.io/en/latest/"
keywords = ["SystemVerilog", "Verilog", "Hardware", "IP", "cocotb"]
keywords = ["SystemVerilog", "Verilog", "Hardware", "IP", "Cocotb"]
readme = "README.rst"
classifiers = [
"Topic :: System :: Hardware",
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4 changes: 2 additions & 2 deletions tests/counters/test_binary_counter.py
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Expand Up @@ -18,9 +18,9 @@ async def cocotb_test_binary_counter(dut):
cocotb.fork(Clock(dut.clk, 2).start())

# reset
dut.aresetn <= 0
dut.aresetn.value = 0
await FallingEdge(dut.clk)
dut.aresetn <= 1
dut.aresetn.value = 1

# increment through all possible counter states
for i in range(2 ** n):
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2 changes: 1 addition & 1 deletion tests/decoders/test_bcd_decoder.py
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Expand Up @@ -15,6 +15,6 @@ async def cocotb_test_bcd_decoder(dut):
n = int(dut.N)

for i in range(10 ** n):
dut.i_bcd <= int(str(int(i)), 16)
dut.i_bcd.value = int(str(int(i)), 16)
await Timer(1)
assert dut.o_bin == i
2 changes: 1 addition & 1 deletion tests/encoders/test_bcd_encoder.py
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,6 @@ async def cocotb_test_bcd_encoder(dut):
n = int(dut.N)

for i in range(2 ** n):
dut.i_bin <= i
dut.i_bin.value = i
await Timer(1)
assert dut.o_bcd == int(str(int(dut.i_bin)), 16)
10 changes: 5 additions & 5 deletions tests/latches/test_sr_latch.py
Original file line number Diff line number Diff line change
Expand Up @@ -12,19 +12,19 @@ def test_sr_latch(pytestconfig):
async def cocotb_test_sr_latch(dut):
"""SR Latch test"""

dut.s <= 0
dut.r <= 0
dut.s.value = 0
dut.r.value = 0
await Timer(1)

dut.s <= 1
dut.s.value = 1
await Timer(1)
assert dut.q == 1
assert dut.q_n == 0

dut.s <= 0
dut.s.value = 0
await Timer(1)

dut.r <= 1
dut.r.value = 1
await Timer(1)
assert dut.q == 0
assert dut.q_n == 1
6 changes: 3 additions & 3 deletions tests/math/test_full_adder.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,9 @@ async def cocotb_test_full_adder(dut):
o_sum = i_a ^ i_b ^ i_carry
o_carry = ((i_a | i_b) & i_carry) | (i_a & i_b)

dut.i_a <= i_a
dut.i_b <= i_b
dut.i_carry <= i_carry
dut.i_a.value = i_a
dut.i_b.value = i_b
dut.i_carry.value = i_carry
await Timer(1)
assert dut.o_sum == o_sum
assert dut.o_carry == o_carry
4 changes: 2 additions & 2 deletions tests/math/test_half_adder.py
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Expand Up @@ -18,8 +18,8 @@ async def cocotb_test_half_adder(dut):
o_sum = i_a ^ i_b
o_carry = i_a & i_b

dut.i_a <= i_a
dut.i_b <= i_b
dut.i_a.value = i_a
dut.i_b.value = i_b
await Timer(1)
assert dut.o_sum == o_sum
assert dut.o_carry == o_carry
4 changes: 2 additions & 2 deletions tests/muxes/test_onehot_mux.py
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Expand Up @@ -19,9 +19,9 @@ async def cocotb_test_onehot_mux(dut):
dut_i = 0
for i in range(n):
dut_i |= (i % dw) << (i * dw)
dut.i <= dut_i
dut.i.value = dut_i

for i in range(n):
dut.sel <= 1 << i
dut.sel.value = 1 << i
await Timer(1)
assert i % dw == int(dut.o)

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