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uart_ice40

The iCE40 FPGAs are small, with 1k and 10k 4-input LUTs. Hence the implementation size of constructions really matters. This project is a minimal UART specifically written for iCE40.

Status

• Compilation: Code compiles using Lattice Icecube2/Synplify. Compiles with Yosys (contribution by gthommasen).
• Simulation: Close to complete.
• Hardware: 115200 tested on iCEstick, but must be retested.
• Documentation, see main documentation file

Plans

• There are some corner cases to simulate. Documentation to be enhanced with a few screendumps from gtkwave.
• This will not happen anytime soon, as I want to use the module for a while.