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Add support for ESP32 and RISC-V #1459
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This is ready for review! |
@ellenhp Greetings, I have a rv64gc linux board I can use to test this, would it just be a case of checking out your branch and something like |
https://gist.github.com/sajattack/57f413217325d53446c550dd0cc830c7 Well done, hopefully that helps get this merged. |
Yeah I'm not sure how hopeful I am of this getting looked at but hopefully the patch is useful for someone :) |
@briansmith sorry for the ping, but is there anything here that you're interested in reviewing/merging or would you like me to close this? |
I ran
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Closing this for now. Feel free to salvage, rebase, etc, but I'm not going to put effort into getting this merged anymore because the maintainer clearly doesn't want it. |
Thank you very much for the PR @ellenhp. It's a shame we didn't get a response here. For the time being, I've forked and applied your patch in this repo: https://github.com/esp-rs-compat/ring for all those who still need to use it. Espressif will most likely try to get this patch upstreamed again in the near future. |
Related to #1436 and #1297
Fixes #1455
Will likely address #1419 but I don't know for sure.
A few points:
crypto/internal.h
. Since we treat warnings as errors I needed to add a way to disable the-Winline
flag.cargo test
. Let me know if this is a blocker and I'll figure out how to at least make the tests work on RISC-V. I think linux on RISC-V would work in qemu or something.