This is a single cycle RISC CPU, the first try for the git.
000000001010_00000_000_00001_0010011 // addi x1, x0, 20 // x1 = x0 + 10
000000011001_00000_000_00010_0010011 // addi x2, x0, 35 // x2 = x0 + 25
000000110010_00000_000_00011_0010011 // addi x3, x0, 49 // x3 = x0 + 50
0000000_00010_00001_000_00100_0110011 // add x4, x1, x2 // x4 = x1 + x2
0100000_00001_00010_000_00101_0110011 // sub x5, x2, x1 // x5 = x2 - x1
0000000_00010_00001_111_00110_0110011 // and x6, x1, x2 // x6 = x1 & x2
0000000_00010_00001_110_00111_0110011 // or x7, x1, x2 // x7 = x1 & x2
0000000_00101_00000_010_00000_0100011 // sw x5, 0(x0) //Mem(0+x0) = x5
0000000_00110_00000_010_00100_0100011 // sw x6, 4(x0) //Mem(4+x0) = x6
0000000_00100_00000_010_01000_0100011 // sw x4, 8(x0) //Mem(8+x0) = x4
000000001000_00000_010_00111_0000011 // lw x7, 4(x1) //x7 = Mem(8+x0)