Add test cases and fix args order

cea-sec · May 22, 2020 · fb31ac0 · fb31ac0
1 parent 30cee45
commit fb31ac0
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Showing 3 changed files with 33 additions and 12 deletions.
diff --git a/miasm/arch/mips32/arch.py b/miasm/arch/mips32/arch.py
@@ -795,26 +795,26 @@ class bs_cond_mod(cpu.bs_mod_name):
          [rs, rt])
 
 mips32op("clz",     [cpu.bs('011100'), rs, rt, rd, cpu.bs('00000'), cpu.bs('100000')],
-        [rs, rd])
+        [rd, rs])
 mips32op("clz",     [cpu.bs('000000'), rs, cpu.bs('00000'), rd, cpu.bs('00001010000')],
-        [rs, rd])
+        [rd, rs])
 
-mips32op("ll",      [cpu.bs('110000'), base, rt, s16imm_noarg], [base, rt])
-mips32op("ll",      [cpu.bs('011111'), base, rt, s09imm_noarg, cpu.bs('0110110')], [base, rt])
+mips32op("ll",      [cpu.bs('110000'), base, rt, s16imm_noarg], [rt, base])
+mips32op("ll",      [cpu.bs('011111'), base, rt, s09imm_noarg, cpu.bs('0110110')], [rt, base])
 
-mips32op("sc",      [cpu.bs('111000'), base, rt, s16imm_noarg], [base, rt])
-mips32op("sc",      [cpu.bs('011111'), base, rt, s09imm_noarg, cpu.bs('0'), cpu.bs('100110')], [base, rt])
+mips32op("sc",      [cpu.bs('111000'), base, rt, s16imm_noarg], [rt, base])
+mips32op("sc",      [cpu.bs('011111'), base, rt, s09imm_noarg, cpu.bs('0'), cpu.bs('100110')], [rt, base])
 
 mips32op("sync",    [cpu.bs('000000000000000000000'), stype, cpu.bs('001111')], [stype])
 
-mips32op("pref",    [cpu.bs('110011'), base, hint_pref, s16imm_noarg], [base, hint_pref])
-mips32op("pref",    [cpu.bs('011111'), base, hint_pref, s09imm_noarg, cpu.bs('0110101')], [base, hint_pref])
+mips32op("pref",    [cpu.bs('110011'), base, hint_pref, s16imm_noarg], [hint_pref, base])
+mips32op("pref",    [cpu.bs('011111'), base, hint_pref, s09imm_noarg, cpu.bs('0110101')], [hint_pref, base])
 
 mips32op("tlbwr",   [cpu.bs('01000010000000000000000000000110')], [])
 mips32op("tlbr",    [cpu.bs('01000010000000000000000000000001')], [])
 
-mips32op("cache",   [cpu.bs('101111'), base, oper, s16imm_noarg], [base, oper])
-mips32op("cache",   [cpu.bs('011111'), base, oper, s09imm_noarg, cpu.bs('0100101')], [base, oper])
+mips32op("cache",   [cpu.bs('101111'), base, oper, s16imm_noarg], [oper, base])
+mips32op("cache",   [cpu.bs('011111'), base, oper, s09imm_noarg, cpu.bs('0100101')], [oper, base])
 
 mips32op("eret",    [cpu.bs('01000010000000000000000000011000')], [])
 

diff --git a/miasm/arch/mips32/sem.py b/miasm/arch/mips32/sem.py
@@ -511,8 +511,8 @@ def ehb(arg1):
 
 @sbuild.parse
 def sc(arg1, arg2):
-    arg1 = arg2;
-    arg2 = ExprInt(0x1, 32)
+    arg2 = arg1;
+    arg1 = ExprInt(0x1, 32)
 
 @sbuild.parse
 def mthi(arg1):

diff --git a/test/arch/mips32/arch.py b/test/arch/mips32/arch.py
@@ -231,6 +231,27 @@
      "45020008"),
     ("XXXXXXXX    BC1TL      FCC0, 0xB8",
      "4503002D"),
+
+    ("XXXXXXXX    CLZ        K0, K1",
+     "737AD020"),
+
+    ("XXXXXXXX    LL         A0, 0x123(A1)",
+     "C0A40123"),
+    ("XXXXXXXX    SC         A1, 0x123(A0)",
+     "E0850123"),
+
+    ("XXXXXXXX    SYNC       0x19",
+     "0000064F"),
+    ("XXXXXXXX    TLBR       ",
+     "42000001"),
+
+    ("XXXXXXXX    ERET       ",
+     "42000018"),
+
+    ("XXXXXXXX    MTHI       A0",
+     "00800011"),
+    ("XXXXXXXX    MTLO       A1",
+     "00A00013")
 ]