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Update vendored OpenTitan entropy IPs to Earlgrey-PROD-M5 #665

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[csrng] update integration tests for new CSRNG register maps
Signed-off-by: Gary Guo <[email protected]>
nbdd0121 committed Dec 16, 2024

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This commit was created on GitHub.com and signed with GitHub’s verified signature.
commit 050f8c0f08ab92dcd5f8c6047e8d2edc8abfb88f
29 changes: 15 additions & 14 deletions src/csrng/tb/csrng_tb.sv
Original file line number Diff line number Diff line change
@@ -49,16 +49,17 @@ module csrng_tb
parameter ADDR_REGWEN = 32'h10;
parameter ADDR_CTRL = 32'h14;
parameter ADDR_CMD_REQ = 32'h18;
parameter ADDR_SW_CMD_STS = 32'h1c;
parameter ADDR_GENBITS_VLD = 32'h20;
parameter ADDR_GENBITS = 32'h24;
parameter ADDR_INT_STATE_NUM = 32'h28;
parameter ADDR_INT_STATE_VAL = 32'h2c;
parameter ADDR_HW_EXC_STS = 32'h30;
parameter ADDR_RECOV_ALERT_STS = 32'h34;
parameter ADDR_ERR_CODE = 32'h38;
parameter ADDR_ERR_CODE_TEST = 32'h3c;
parameter ADDR_MAIN_SM_STATE = 32'h40;
parameter ADDR_RESEED_INTERVAL = 32'h1c;
parameter ADDR_SW_CMD_STS = 32'h20;
parameter ADDR_GENBITS_VLD = 32'h24;
parameter ADDR_GENBITS = 32'h28;
parameter ADDR_INT_STATE_NUM = 32'h2c;
parameter ADDR_INT_STATE_VAL = 32'h30;
parameter ADDR_HW_EXC_STS = 32'h34;
parameter ADDR_RECOV_ALERT_STS = 32'h38;
parameter ADDR_ERR_CODE = 32'h3c;
parameter ADDR_ERR_CODE_TEST = 32'h40;
parameter ADDR_MAIN_SM_STATE = 32'h44;

parameter AHB_HTRANS_IDLE = 0;
parameter AHB_HTRANS_BUSY = 1;
@@ -361,7 +362,7 @@ module csrng_tb
$display("Uninitiate Command");
write_single_word(ADDR_CMD_REQ, 32'h0905);
repeat (200) @(posedge clk_tb);
poll_register_value(ADDR_SW_CMD_STS, 32'h1);
poll_register_value(ADDR_SW_CMD_STS, 32'h6);

$display("Initiate Command - Writing 48B of seed");
write_single_word(ADDR_CMD_REQ, 32'h06C1);
@@ -378,7 +379,7 @@ module csrng_tb
write_single_word(ADDR_CMD_REQ, 32'ha468649e);
write_single_word(ADDR_CMD_REQ, 32'hdf5d73fa);

poll_register_value(ADDR_SW_CMD_STS, 32'h1);
poll_register_value(ADDR_SW_CMD_STS, 32'h6);

$display("Generate Command - 512b");
write_single_word(ADDR_CMD_REQ, 32'h4903);
@@ -408,7 +409,7 @@ module csrng_tb
read_and_compare(ADDR_GENBITS, 32'hc58a553e);
read_and_compare(ADDR_GENBITS, 32'h5d6e1012);

poll_register_value(ADDR_SW_CMD_STS, 32'h1);
poll_register_value(ADDR_SW_CMD_STS, 32'h6);

$display("Generate Command - 512b");
write_single_word(ADDR_CMD_REQ, 32'h4903);
@@ -438,7 +439,7 @@ module csrng_tb
read_and_compare(ADDR_GENBITS, 32'hdb17514c);
read_and_compare(ADDR_GENBITS, 32'ha43c41b7);

poll_register_value(ADDR_SW_CMD_STS, 32'h1);
poll_register_value(ADDR_SW_CMD_STS, 32'h6);

endtask // run_smoke_test

44 changes: 23 additions & 21 deletions src/integration/rtl/caliptra_reg.h
Original file line number Diff line number Diff line change
@@ -4579,34 +4579,36 @@
#define CSRNG_REG_CMD_REQ_FLAG0_MASK (0xf00)
#define CSRNG_REG_CMD_REQ_GLEN_LOW (12)
#define CSRNG_REG_CMD_REQ_GLEN_MASK (0x1fff000)
#define CLP_CSRNG_REG_SW_CMD_STS (0x2000201c)
#define CSRNG_REG_SW_CMD_STS (0x1c)
#define CLP_CSRNG_REG_RESEED_INTERVAL (0x2000201c)
#define CSRNG_REG_RESEED_INTERVAL (0x1c)
#define CLP_CSRNG_REG_SW_CMD_STS (0x20002020)
#define CSRNG_REG_SW_CMD_STS (0x20)
#define CSRNG_REG_SW_CMD_STS_CMD_RDY_LOW (1)
#define CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK (0x2)
#define CSRNG_REG_SW_CMD_STS_CMD_ACK_LOW (2)
#define CSRNG_REG_SW_CMD_STS_CMD_ACK_MASK (0x4)
#define CSRNG_REG_SW_CMD_STS_CMD_STS_LOW (3)
#define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (0x18)
#define CLP_CSRNG_REG_GENBITS_VLD (0x20002020)
#define CSRNG_REG_GENBITS_VLD (0x20)
#define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (0x38)
#define CLP_CSRNG_REG_GENBITS_VLD (0x20002024)
#define CSRNG_REG_GENBITS_VLD (0x24)
#define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_LOW (0)
#define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_MASK (0x1)
#define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_LOW (1)
#define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_MASK (0x2)
#define CLP_CSRNG_REG_GENBITS (0x20002024)
#define CSRNG_REG_GENBITS (0x24)
#define CLP_CSRNG_REG_INT_STATE_NUM (0x20002028)
#define CSRNG_REG_INT_STATE_NUM (0x28)
#define CLP_CSRNG_REG_GENBITS (0x20002028)
#define CSRNG_REG_GENBITS (0x28)
#define CLP_CSRNG_REG_INT_STATE_NUM (0x2000202c)
#define CSRNG_REG_INT_STATE_NUM (0x2c)
#define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_LOW (0)
#define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_MASK (0xf)
#define CLP_CSRNG_REG_INT_STATE_VAL (0x2000202c)
#define CSRNG_REG_INT_STATE_VAL (0x2c)
#define CLP_CSRNG_REG_HW_EXC_STS (0x20002030)
#define CSRNG_REG_HW_EXC_STS (0x30)
#define CLP_CSRNG_REG_INT_STATE_VAL (0x20002030)
#define CSRNG_REG_INT_STATE_VAL (0x30)
#define CLP_CSRNG_REG_HW_EXC_STS (0x20002034)
#define CSRNG_REG_HW_EXC_STS (0x34)
#define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_LOW (0)
#define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_MASK (0xffff)
#define CLP_CSRNG_REG_RECOV_ALERT_STS (0x20002034)
#define CSRNG_REG_RECOV_ALERT_STS (0x34)
#define CLP_CSRNG_REG_RECOV_ALERT_STS (0x20002038)
#define CSRNG_REG_RECOV_ALERT_STS (0x38)
#define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_LOW (0)
#define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK (0x1)
#define CSRNG_REG_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_LOW (1)
@@ -4621,8 +4623,8 @@
#define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_MASK (0x2000)
#define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_INVALID_CMD_SEQ_LOW (14)
#define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_INVALID_CMD_SEQ_MASK (0x4000)
#define CLP_CSRNG_REG_ERR_CODE (0x20002038)
#define CSRNG_REG_ERR_CODE (0x38)
#define CLP_CSRNG_REG_ERR_CODE (0x2000203c)
#define CSRNG_REG_ERR_CODE (0x3c)
#define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_LOW (0)
#define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_MASK (0x1)
#define CSRNG_REG_ERR_CODE_SFIFO_GENBITS_ERR_LOW (1)
@@ -4675,12 +4677,12 @@
#define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_MASK (0x20000000)
#define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30)
#define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_MASK (0x40000000)
#define CLP_CSRNG_REG_ERR_CODE_TEST (0x2000203c)
#define CSRNG_REG_ERR_CODE_TEST (0x3c)
#define CLP_CSRNG_REG_ERR_CODE_TEST (0x20002040)
#define CSRNG_REG_ERR_CODE_TEST (0x40)
#define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0)
#define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (0x1f)
#define CLP_CSRNG_REG_MAIN_SM_STATE (0x20002040)
#define CSRNG_REG_MAIN_SM_STATE (0x40)
#define CLP_CSRNG_REG_MAIN_SM_STATE (0x20002044)
#define CSRNG_REG_MAIN_SM_STATE (0x44)
#define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0)
#define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (0xff)
#define CLP_ENTROPY_SRC_REG_BASE_ADDR (0x20003000)
44 changes: 23 additions & 21 deletions src/integration/rtl/caliptra_reg_defines.svh
Original file line number Diff line number Diff line change
@@ -4579,34 +4579,36 @@
`define CSRNG_REG_CMD_REQ_FLAG0_MASK (32'hf00)
`define CSRNG_REG_CMD_REQ_GLEN_LOW (12)
`define CSRNG_REG_CMD_REQ_GLEN_MASK (32'h1fff000)
`define CLP_CSRNG_REG_SW_CMD_STS (32'h2000201c)
`define CSRNG_REG_SW_CMD_STS (32'h1c)
`define CLP_CSRNG_REG_RESEED_INTERVAL (32'h2000201c)
`define CSRNG_REG_RESEED_INTERVAL (32'h1c)
`define CLP_CSRNG_REG_SW_CMD_STS (32'h20002020)
`define CSRNG_REG_SW_CMD_STS (32'h20)
`define CSRNG_REG_SW_CMD_STS_CMD_RDY_LOW (1)
`define CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK (32'h2)
`define CSRNG_REG_SW_CMD_STS_CMD_ACK_LOW (2)
`define CSRNG_REG_SW_CMD_STS_CMD_ACK_MASK (32'h4)
`define CSRNG_REG_SW_CMD_STS_CMD_STS_LOW (3)
`define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (32'h18)
`define CLP_CSRNG_REG_GENBITS_VLD (32'h20002020)
`define CSRNG_REG_GENBITS_VLD (32'h20)
`define CSRNG_REG_SW_CMD_STS_CMD_STS_MASK (32'h38)
`define CLP_CSRNG_REG_GENBITS_VLD (32'h20002024)
`define CSRNG_REG_GENBITS_VLD (32'h24)
`define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_LOW (0)
`define CSRNG_REG_GENBITS_VLD_GENBITS_VLD_MASK (32'h1)
`define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_LOW (1)
`define CSRNG_REG_GENBITS_VLD_GENBITS_FIPS_MASK (32'h2)
`define CLP_CSRNG_REG_GENBITS (32'h20002024)
`define CSRNG_REG_GENBITS (32'h24)
`define CLP_CSRNG_REG_INT_STATE_NUM (32'h20002028)
`define CSRNG_REG_INT_STATE_NUM (32'h28)
`define CLP_CSRNG_REG_GENBITS (32'h20002028)
`define CSRNG_REG_GENBITS (32'h28)
`define CLP_CSRNG_REG_INT_STATE_NUM (32'h2000202c)
`define CSRNG_REG_INT_STATE_NUM (32'h2c)
`define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_LOW (0)
`define CSRNG_REG_INT_STATE_NUM_INT_STATE_NUM_MASK (32'hf)
`define CLP_CSRNG_REG_INT_STATE_VAL (32'h2000202c)
`define CSRNG_REG_INT_STATE_VAL (32'h2c)
`define CLP_CSRNG_REG_HW_EXC_STS (32'h20002030)
`define CSRNG_REG_HW_EXC_STS (32'h30)
`define CLP_CSRNG_REG_INT_STATE_VAL (32'h20002030)
`define CSRNG_REG_INT_STATE_VAL (32'h30)
`define CLP_CSRNG_REG_HW_EXC_STS (32'h20002034)
`define CSRNG_REG_HW_EXC_STS (32'h34)
`define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_LOW (0)
`define CSRNG_REG_HW_EXC_STS_HW_EXC_STS_MASK (32'hffff)
`define CLP_CSRNG_REG_RECOV_ALERT_STS (32'h20002034)
`define CSRNG_REG_RECOV_ALERT_STS (32'h34)
`define CLP_CSRNG_REG_RECOV_ALERT_STS (32'h20002038)
`define CSRNG_REG_RECOV_ALERT_STS (32'h38)
`define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_LOW (0)
`define CSRNG_REG_RECOV_ALERT_STS_ENABLE_FIELD_ALERT_MASK (32'h1)
`define CSRNG_REG_RECOV_ALERT_STS_SW_APP_ENABLE_FIELD_ALERT_LOW (1)
@@ -4621,8 +4623,8 @@
`define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_ALERT_MASK (32'h2000)
`define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_INVALID_CMD_SEQ_LOW (14)
`define CSRNG_REG_RECOV_ALERT_STS_CS_MAIN_SM_INVALID_CMD_SEQ_MASK (32'h4000)
`define CLP_CSRNG_REG_ERR_CODE (32'h20002038)
`define CSRNG_REG_ERR_CODE (32'h38)
`define CLP_CSRNG_REG_ERR_CODE (32'h2000203c)
`define CSRNG_REG_ERR_CODE (32'h3c)
`define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_LOW (0)
`define CSRNG_REG_ERR_CODE_SFIFO_CMD_ERR_MASK (32'h1)
`define CSRNG_REG_ERR_CODE_SFIFO_GENBITS_ERR_LOW (1)
@@ -4675,12 +4677,12 @@
`define CSRNG_REG_ERR_CODE_FIFO_READ_ERR_MASK (32'h20000000)
`define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_LOW (30)
`define CSRNG_REG_ERR_CODE_FIFO_STATE_ERR_MASK (32'h40000000)
`define CLP_CSRNG_REG_ERR_CODE_TEST (32'h2000203c)
`define CSRNG_REG_ERR_CODE_TEST (32'h3c)
`define CLP_CSRNG_REG_ERR_CODE_TEST (32'h20002040)
`define CSRNG_REG_ERR_CODE_TEST (32'h40)
`define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_LOW (0)
`define CSRNG_REG_ERR_CODE_TEST_ERR_CODE_TEST_MASK (32'h1f)
`define CLP_CSRNG_REG_MAIN_SM_STATE (32'h20002040)
`define CSRNG_REG_MAIN_SM_STATE (32'h40)
`define CLP_CSRNG_REG_MAIN_SM_STATE (32'h20002044)
`define CSRNG_REG_MAIN_SM_STATE (32'h44)
`define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_LOW (0)
`define CSRNG_REG_MAIN_SM_STATE_MAIN_SM_STATE_MASK (32'hff)
`define CLP_ENTROPY_SRC_REG_BASE_ADDR (32'h20003000)
8 changes: 4 additions & 4 deletions src/integration/test_suites/smoke_test_trng/smoke_test_trng.c
Original file line number Diff line number Diff line change
@@ -112,7 +112,7 @@ int run_smoke_test() {
printf("Uninitiate Command\n");
lsu_write_32(CLP_CSRNG_REG_CMD_REQ, 0x905);

poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK);
poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK | CSRNG_REG_SW_CMD_STS_CMD_ACK_MASK);

printf("Initiate Command - Writing 48B of seed\n");
lsu_write_32(CLP_CSRNG_REG_CMD_REQ, 0x06C1);
@@ -129,7 +129,7 @@ int run_smoke_test() {
lsu_write_32(CLP_CSRNG_REG_CMD_REQ, 0xa468649e);
lsu_write_32(CLP_CSRNG_REG_CMD_REQ, 0xdf5d73fa);

poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK);
poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK | CSRNG_REG_SW_CMD_STS_CMD_ACK_MASK);

printf("Generate Command - 512b\n");
lsu_write_32(CLP_CSRNG_REG_CMD_REQ, 0x4903);
@@ -158,7 +158,7 @@ int run_smoke_test() {
error += read_and_compare(CLP_CSRNG_REG_GENBITS, 0xc58a553e);
error += read_and_compare(CLP_CSRNG_REG_GENBITS, 0x5d6e1012);

poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK);
poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK | CSRNG_REG_SW_CMD_STS_CMD_ACK_MASK);

printf("Generate Command - 512b\n");
lsu_write_32(CLP_CSRNG_REG_CMD_REQ, 0x4903);
@@ -188,7 +188,7 @@ int run_smoke_test() {
error += read_and_compare(CLP_CSRNG_REG_GENBITS, 0xdb17514c);
error += read_and_compare(CLP_CSRNG_REG_GENBITS, 0xa43c41b7);

poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK);
poll_reg(CLP_CSRNG_REG_SW_CMD_STS, CSRNG_REG_SW_CMD_STS_CMD_RDY_MASK | CSRNG_REG_SW_CMD_STS_CMD_ACK_MASK);

return error;
}