Allow passing defines to symbiflow_synth

chipsalliance · Jun 13, 2024 · b0669bf · b0669bf
1 parent 9c049e2
commit b0669bf
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Showing 2 changed files with 51 additions and 34 deletions.
diff --git a/f4pga/utils/xc7/create_place_constraints.py b/f4pga/utils/xc7/create_place_constraints.py
@@ -1120,11 +1120,13 @@ def main(
         net=Path(net).open("r"),
         vpr_grid_map=vpr_grid_map,
         arch=arch,
-        db_root=environ.get(
-            "DATABASE_DIR", subprocess_run("prjxray-config", capture_output=True).stdout.decode("utf-8").strip()
-        )
-        if db_root is None
-        else db_root,
+        db_root=(
+            environ.get(
+                "DATABASE_DIR", subprocess_run("prjxray-config", capture_output=True).stdout.decode("utf-8").strip()
+            )
+            if db_root is None
+            else db_root
+        ),
         part=part,
         blif=Path(blif).open("r"),
         input=sys.stdin if input is None else Path(input).open("r"),

diff --git a/f4pga/wrappers/sh/xc7/synth.f4pga.sh b/f4pga/wrappers/sh/xc7/synth.f4pga.sh
@@ -24,47 +24,61 @@ TOP=top
 DEVICE="*"
 PART=""
 SURELOG_CMD=()
+DEFINE_LIST=()
 
 VERILOGLIST=0
 XDCLIST=0
 TOPNAME=0
 DEVICENAME=0
 PARTNAME=0
 SURELOG=0
+DEFINES=0
 
 for arg in $@; do
   echo $arg
   case "$arg" in
-    -v|--verilog) VERILOGLIST=1 XDCLIST=0 TOPNAME=0 DEVICENAME=0 PARTNAME=0 SURELOG=0 ;;
-    -x|--xdc)     VERILOGLIST=0 XDCLIST=1 TOPNAME=0 DEVICENAME=0 PARTNAME=0 SURELOG=0 ;;
-    -t|--top)     VERILOGLIST=0 XDCLIST=0 TOPNAME=1 DEVICENAME=0 PARTNAME=0 SURELOG=0 ;;
-    -d|--device)  VERILOGLIST=0 XDCLIST=0 TOPNAME=0 DEVICENAME=1 PARTNAME=0 SURELOG=0 ;;
-    -p|--part)    VERILOGLIST=0 XDCLIST=0 TOPNAME=0 DEVICENAME=0 PARTNAME=1 SURELOG=0 ;;
-    -s|--surelog) VERILOGLIST=0 XDCLIST=0 TOPNAME=0 DEVICENAME=0 PARTNAME=0 SURELOG=1 ;;
-    *)
-      if [ $VERILOGLIST -eq 1 ]; then
-        VERILOG_FILES+=($arg)
-      elif [ $XDCLIST -eq 1 ]; then
-        XDC_FILES+=($arg)
-      elif [ $TOPNAME -eq 1 ]; then
-        TOP=$arg
-      elif [ $DEVICENAME -eq 1 ]; then
-        DEVICE=$arg
-      elif [ $PARTNAME -eq 1 ]; then
-        PART=$arg
-      elif [ $SURELOG -eq 1 ]; then
-        SURELOG_CMD+=($arg)
-      else
-        echo "Usage: synth [-t|--top <top module name> -v|--verilog <Verilog files list> [-x|--xdc <XDC files list>]"
-        echo "             [-d|--device <device type (e.g. artix7)>] [-p|--part <part name>] [-s|--surelog] <parameters to surelog>"
-        echo "note: device and part parameters are required if xdc is passed"
-        exit 1
-      fi
-      ;;
+  -v | --verilog) VERILOGLIST=1 XDCLIST=0 TOPNAME=0 DEVICENAME=0 PARTNAME=0 SURELOG=0 DEFINES=0 ;;
+  -x | --xdc) VERILOGLIST=0 XDCLIST=1 TOPNAME=0 DEVICENAME=0 PARTNAME=0 SURELOG=0 DEFINES=0 ;;
+  -t | --top) VERILOGLIST=0 XDCLIST=0 TOPNAME=1 DEVICENAME=0 PARTNAME=0 SURELOG=0 DEFINES=0 ;;
+  -d | --device) VERILOGLIST=0 XDCLIST=0 TOPNAME=0 DEVICENAME=1 PARTNAME=0 SURELOG=0 DEFINES=0 ;;
+  -p | --part) VERILOGLIST=0 XDCLIST=0 TOPNAME=0 DEVICENAME=0 PARTNAME=1 SURELOG=0 DEFINES=0 ;;
+  -s | --surelog) VERILOGLIST=0 XDCLIST=0 TOPNAME=0 DEVICENAME=0 PARTNAME=0 SURELOG=1 DEFINES=0 ;;
+  -e | --defines) VERILOGLIST=0 XDCLIST=0 TOPNAME=0 DEVICENAME=0 PARTNAME=0 SURELOG=0 DEFINES=1 ;;
+  *)
+    if [ $VERILOGLIST -eq 1 ]; then
+      VERILOG_FILES+=($arg)
+    elif [ $XDCLIST -eq 1 ]; then
+      XDC_FILES+=($arg)
+    elif [ $TOPNAME -eq 1 ]; then
+      TOP=$arg
+    elif [ $DEVICENAME -eq 1 ]; then
+      DEVICE=$arg
+    elif [ $PARTNAME -eq 1 ]; then
+      PART=$arg
+    elif [ $SURELOG -eq 1 ]; then
+      SURELOG_CMD+=($arg)
+    elif [ $DEFINES -eq 1 ]; then
+      DEFINE_LIST+=($arg)
+    else
+      echo "Usage: synth [-t|--top <top module name> -v|--verilog <Verilog files list> [-x|--xdc <XDC files list>]"
+      echo "             [-d|--device <device type (e.g. artix7)>] [-p|--part <part name>] [-s|--surelog] <parameters to surelog>"
+      echo "note: device and part parameters are required if xdc is passed"
+      exit 1
+    fi
+    ;;
   esac
 done
 
-if [ ${#VERILOG_FILES[@]} -eq 0 ]; then echo "Please provide at least one Verilog file"; exit 1; fi
+if [ ${#VERILOG_FILES[@]} -eq 0 ]; then
+  echo "Please provide at least one Verilog file"
+  exit 1
+fi
+DEFINE_ARGS=()
+if [ ${#DEFINE_LIST[@]} -ne 0 ]; then
+  for define in "${DEFINE_LIST[@]}"; do
+    DEFINE_ARGS+=("-D$define")
+  done
+fi
 
 export TOP="${TOP}"
 export USE_ROI='FALSE'
@@ -74,7 +88,7 @@ export OUT_SDC="${TOP}.sdc"
 export SYNTH_JSON="${TOP}_io.json"
 export OUT_SYNTH_V="${TOP}_synth.v"
 export OUT_EBLIF="${TOP}.eblif"
-export PART_JSON=`realpath ${DATABASE_DIR:-$(prjxray-config)}/$DEVICE/$PART/part.json`
+export PART_JSON=$(realpath ${DATABASE_DIR:-$(prjxray-config)}/$DEVICE/$PART/part.json)
 export OUT_FASM_EXTRA="${TOP}_fasm_extra.fasm"
 export PYTHON3="${PYTHON3:-$(which python3)}"
 
@@ -84,7 +98,8 @@ if [ -n "$SURELOG_CMD" ]; then
   yosys_read_cmds="plugin -i systemverilog; read_systemverilog ${SURELOG_CMD[*]} ${VERILOG_FILES[*]}"
   yosys_files=""
 fi
-yosys \
+echo yosys \
   -p "$yosys_read_cmds; tcl $(python3 -m f4pga.wrappers.tcl)" \
   -l "${TOP}_synth.log" \
+  "${DEFINE_ARGS[*]}" \
   $yosys_files