Add ice40 flow

f4pga/aux/tool_data/yosys/scripts/vendor/lattice/ice40/synth.tcl

@@ -0,0 +1,51 @@
+# Copyright (C) 2022 F4PGA Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+yosys -import
+
+plugin -i fasm
+
+# Import the commands from the plugins to the tcl interpreter
+yosys -import
+
+f4pga value    top
+f4pga value    part_name
+f4pga value    yosys_plugins?
+f4pga take     sources
+f4pga take     build_dir
+f4pga produce  json            ${f4pga_build_dir}/${f4pga_top}.json      -meta "Yosys JSON netlist"
+f4pga produce  synth_v         ${f4pga_build_dir}/${f4pga_top}_premap.v  -meta "Pre-technology mapped structural verilog"
+
+if { [contains $f4pga_yosys_plugins uhdm] } {
+    foreach {sysverilog_source} $f4pga_sources {
+        read_verilog_with_uhdm $surelog_cmd $sysverilog_source
+    }    
+} else {
+    foreach {verilog_source} $f4pga_sources {
+        read_verilog $verilog_source
+    }    
+}
+
+synth_ice40 -nocarry
+
+opt_expr -undriven
+opt_clean
+
+attrmap -remove hdlname
+
+setundef -zero -params
+write_json $f4pga_json
+write_verilog $f4pga_synth_v

f4pga/flows/part_db.yml

@@ -45,3 +45,52 @@ ql-k4n8_slow:
 
 ql-k4n8_fast:
   - K4N8_FAST
+
+ice40:
+  - ICE40LP1K-CB121
+  - ICE40LP1K-CB81
+  - ICE40LP4K-CM225
+  - ICE40LP8K-CM225
+  - ICE40LP1K-CM121
+  - ICE40LP4K-CM121
+  - ICE40LP8K-CM121
+  - ICE40LP384-CM36
+  - ICE40LP1K-CM36
+  - ICE40LP384-CM49
+  - ICE40LP1K-CM49
+  - ICE40LP1K-CM81
+  - ICE40LP4K-CM81
+  - ICE40LP8K-CM81
+  - ICE40LP1K-QN84
+  - ICE40LP384-SG32
+  - ICE40LP640-SWG16
+  - ICE40LP1K-SWG16
+  - ICE40LP384-VQ100
+  - ICE40LP640-VQ100
+  - ICE40LP1K-VQ100
+  - ICE40LP4K-VQ100
+  - ICE40LP8K-VQ100
+  - ICE40HX1K-CB132
+  - ICE40HX4K-CB132
+  - ICE40HX8K-CB132
+  - ICE40HX1K-VQ100
+  - ICE40HX1K-TQ144
+  - ICE40HX4K-TQ144
+  - ICE40HX8K-CM225
+  - ICE40HX8K-CT256
+  - ICE40UP3K-UWG30
+  - ICE40UP3K-SG48
+  - ICE40UP5K-UWG30
+  - ICE40UP5K-SG48
+  - ICE40UL640-SWG16
+  - ICE40UL640-CM36
+  - ICE40UL1K-CM36
+  - ICE5LP1K-SWG36
+  - ICE5LP2K-SWG36
+  - ICE5LP4K-SWG36
+  - ICE5LP1K-CM36
+  - ICE5LP2K-CM36
+  - ICE5LP4K-CM36
+  - ICE5LP1K-SG48
+  - ICE5LP2K-SG48
+  - ICE5LP4K-SG4

f4pga/flows/platforms.yml

@@ -180,6 +180,41 @@ xc7a200t:
     vpr_options: *xc7-vpr_options
 
 
+ice40:
+
+  values:
+    nextpnr_options:
+      hx1k: true
+
+  stages:
+    mk_build_dir:
+      module: 'common:mkdirs'
+      params:
+        build_dir: build/${device}
+    synth:
+      module: 'common:yosys'
+      params:
+        tcl_script: "${auxDir}/tool_data/yosys/scripts/vendor/lattice/ice40/synth.tcl"
+    pnr:
+      module: 'ice40:nextpnr'
+      values:
+        placer: heap
+        router: router1
+    bitstream:
+      module: 'common:generic_script_wrapper'
+      params:
+        stage_name: bitstream
+        script: icepack
+        outputs:
+          bitstream:
+            mode: file
+            file: "${:ice_asm[noext]}.bit"
+            target: "${:ice_asm[noext]}.bit"
+        inputs:
+          "#1": "${:ice_asm}"
+          "#2": "${:ice_asm[noext]}.bit"
+
+
 ql-eos-s3:
 
   values: