[patch] Probes Section cleanup (#154)

Co-authored-by: Megan Wachs <[email protected]>

spec.md

@@ -2269,8 +2269,7 @@ Probe<UInt<8>, A.B>     ; A.B is a layer
 RWProbe<UInt<8>, A.B>
 ```
 
-Probes are generally lowered to hierarchical names in Verilog.
-For details, see the FIRRTL ABI Specification.
+For details on how probes are lowered, see the FIRRTL ABI Specification.
 
 ## External Modules
 
@@ -2302,7 +2301,7 @@ FIRRTL allows probes to be passed through ports.
 However, due to the limitations of Verilog, there is an important restriction on where they may be used.
 
 A module which only sends probes up towards its parent via output ports have no restriction.
-However, when a module receives a probe from its parent through an input port, you may not use it in a `read`{.firrtl} expression nor may you force it if the circuit component it refences does not live in a module that is a descendent of the current module.
+However, when a module receives a probe from its parent through an input port, it may not use it in a `read`{.firrtl} expression nor may it force it if the circuit component it references does not live in a module that is a descendent of the current module.
 
 For more information on the how probes are lowered, see the FIRRTL ABI Specification.