Remove unintended truncation behavior

[darthscsi]

truncation was intended to be limited to partial connect, not connect. This was changed 5 months ago.

[seldridge]

Truncation was always the behavior of all FIRRTL compilers even when the spec said differently. 🥲 It's great that we can finally change this.

Please add a [major] marker and update the revision history. I can get this into the 3.0.0 release.

[seldridge]

The background here being that all FIRRTL compilers never correctly implemented the "connect does not truncate" behavior. I removed the spec fan-fiction here and opted for the gritty reality. I.e., the following has always, unfortunately compiled:

circuit Foo:
  module Foo:
    input a: UInt<2>
    output b: UInt<1>

    b <= a

To the following Verilog:

module Foo(
  input  [1:0] a,
  output       b
);

  assign b = a[0];
endmodule