v1.2.0-RC1

API Modification

(#952) Add foreach as alternative to map

(#1107) Remove deprecated ComponentName from CombinationalPath annotation

Fix

(#854) Binding support - load memory from file
Binding support

(#868) Make RemoveWires properly include registers in dependency graph
Respect register references in RemoveWires

(#876) Fix NoDedupMem to be cognizant of Module scope

(#883) Filter resource file names to avoid including the same file multiple times.

(#901) Use "" for Inline Name Mangling, Respect Namespaces
Inlining uses "", respects namespaces
Make some Uniquify methods private [firrtl]
Add cloneUnderlying method to Namespace

(#909) Verilog renaming uses "_", works on whole AST
Refactor VerilogRename -> RemoveKeywordCollisions

(#924) Fix TRAVIS_COMMIT_RANGE in .run_chisel_tests, replace ... with ..

(#936) Fix bug in TargetDirAnnotation compatibility

(#963) Remove side effect from DiGraph sum
Remove side effect from DiGraph summation

(#976) Fix NoneCompiler outputForm
Require transforms.size >= 1 for Compilers
Use IdentityTransform to construct NoneCompiler
Add IdentityTransform

(#987) Fix grouping
Fix GroupComponents to work with unused components
Make GroupComponents run ResolveKinds

(#989) Avoid enforcing time constrains during coverage tests.

(#992) Constant Propagate dshl and dshr with constant amounts
Suppress unchecked warning in Constant Propagation
Keep constant propagating expressions until done optimizing

(#1078) Add register init to RemoveWires dependencies

(#1135) Add ExpandConnects to TopWiringTransform fixup

Feature

(#548) Run CheckHighForm after all non-emitter transforms in firrtl tests

(#833) Support for load memory annotations in chisel

(#848) Make Scala 2.12.4 the default.

(#849) Constant prop add

(#851) Combine cats

(#855) Use LinkedHashSet in propagateAnnotations

(#858) Fix Travis

(#859) allowing overrides to $random

(#861) add link to repo for firrtl syntax highlighting in sublime text 3

(#864) Update DontTouchAnnotation not found error message

(#865) Instance Annotations

(#867) Stop reporting exceptions in custom transformations as internal errors

(#869) Add targetDirName test

(#872) Allow the #delay before random initialization to be overridden

(#874) Emit Verilog Comments

(#875) [F764.1] Bump scopt from 3.6.0 -> 3.7.0
Bump scopt from 3.6.0 -> 3.7.0

(#877) [F764.2] Easy conversion of String => LogLevel.value
Add LogLevel apply for String => LogLevel.Value

(#878) [F764.3] Add explicit SystemVerilogCompiler class
Add SystemVerilogCompiler class

(#879) [F764.5] Add firrtl.options package, but do not use
Add firrtl.options tests
Add firrtl.options

(#885) Bug Fixes in TopWiring

(#888) Do not remove ExtMods with no ports by default

(#889) Another TopWiring Bug Fix (Multi-Level Annotations)

(#894) Number all code examples & add specification build to Makefile

(#895) Add CODEOWNERS file

(#898) Enforce port uniqueness in Chirrtl/High Checks

(#900) Add Utils.expandPrefixes as Prefix Unique helper

(#903) add BlackBoxPathAnno

(#915) Added reference to ICCAD paper

(#918) Don't include verilog header files in "FileList" for VCS/Verilator.

(#919) [F764.6] Add, but do not use Options-mirroring Annotations
Make ClockListAnnotation a RegisteredTransform
Make InlineInstances a RegisteredTransform
Make CheckCombLoops a RegisteredTransform
Make DeadCodeElimination a RegisteredTransform
Add MemLibOptions RegisteredLibrary
Make ReplSeqMem mixin HasScoptOptions
Make InferReadWrite mixin HasScoptOptions
Add FirrtlOptions

(#921) Better error message on missing BlackBox resource

(#925) Revert "Instance Annotations"
Revert "Instance Annotations (#865)"

(#926) Instance Annotations, Try No. 2
Instance Annotations

(#927) Fix $TRAVIS_COMMIT_RANGE

(#928) Dont append to lists
Remove all uses of get_flip and deprecate
Use Vector instead of List for bulk renaming in RenameMap
Speed up LowerTypes by replacing foldLeft + List appends with flatMap
Speed up ExpandWhens by replacing foldLeft + List appends with flatMap
Speed up create_exps by replacing foldLeft + List appends with flatMap
Speed up ExpandConnects by replacing foldLeft + List appends with flatMap

(#930) fix renaming of port annotations in Uniquify
Fix renaming in UniquifyPorts

(#931) Update commandline sbt publishLocal

(#932) Better error message for UninferredWidth exception
Add prettyPrint method to Target

(#938) Add FIRRTL logo to repo and README

(#940) Bump sbt to 1.2.6; update dependencies

(#942) Memoize type of instance refs in RemoveKeywordCollisions

(#945) Change firrtl.options API, add Phase

(#946) Remove firrtl.altIR package

(#949) Make return types of utility functions more specific

(#953) Add "none" compiler

(#954) Replace Mappers with Foreachers in several passes

(#956) Add Width Constraints with Annotations

(#958) Fix bug in dedup where lots of annotations could prevent dedup

(#959) Bump SBT from 1.2.6 to 1.2.7 to fix partial recompilation issue

(#961) Small convenience tweaks to IR/WIR APIs

(#962) Enhance CheckCombLoops to support annotated ExtModule paths

(#967) Fix renaming of annotations with paths

(#969) [Top Wiring] Expand top wiring to work on aggregates

(#975) Give better error when mport references non-existant memory.

(#980) Performance fix of Uniquify for deep bundles

(#982) Update documentation links

(#984) Correctly handle dots in loaded memory paths

(#994) Improve Shl codegen; eliminate Shlw WIR node

(#996) Remove ghpages plugin

(#999) Bump copyright year

(#1000) Attempt to deal with timing vagaries in UniquifySpec.quicklyrenamedeepbundles

(#1001) typo fix

(#1002) Fork all sbt tasks
Fork all sbt test and run tasks

(#1003) Add MidFIRRTL spec

(#1004) Add "mverilog" Compiler Option, MinimumVerilogEmitter
Do Shr constant propagation in Legalize
Add RemoveValidIf to -X mverilog
Add "mverilog" and "sverilog" DriverSpec tests
Add "mverilog" Compiler Option, Compiler Fixes

(#1005) Stage/Phase
Add ShellOption, DeletedWrapper
OptionsView/Viewer typeclass canonicalizations
Add tests for Annotations/Options refactor
Add FirrtlStage, make Driver compatibility layer
Improve registered library help text

(#1006) Use default test_run_dir for more DriverSpec tests.

(#1008) Use apache commons for string escaping instead of reflection

(#1009) Missed constprop opportunity

(#1010) Mem helpers

(#1011) Asynchronous Reset

(#1012) Correct Kind info from #1010

(#1014) Fix typo for -c: compiler -> circuit

(#1023) Don't let the main module become deduped out of existence.

(#1024) Prevent Flatten from stripping all annotations

(#1025) No time left for you - quickly rename deep bundles still occasionally fails.

(#1026) Added mergify configuration

(#1027) Added mergify badge to README

(#1029) Bump yosys to 0.8

(#1030) Change mergify to just require an approval

(#1031) Detect and error on registers with flip in type

(#1032) Fix almost all scaladoc warnings, add source links
Add GitHub source links to Scaladoc
Fix almost all Scaladoc warnings

(#1034) Create a simple generic GraphViz renderer for DiGraph

(#1035) Add --nodedup option to facilitate FIRRTL to verilog regression testing.

(#1039) [ExpandWhens] Don't create nodes to hold Muxes with >0 void cases

(#1041) Add a data structure for memory conf reading and writing

(#1043) Make mergify run when no reviews request changes

(#1046) Advertise FIRRTL grammar support in Atom

(#1052) More constprop on muxes

(#1056) Add serialization support for LoadMemoryFileType in LoadMemoryAnnotation

(#1058) Convert the RemoveAccesses object into a class.

(#1060) Fix error reading empty MemConf strings
Designs with no SeqMems should produce empty MemConf strings, and this should be parsable without excepting

(#1063) Correct a typo in spec.tex

(#1065) DCE printf and stop statements with constant-0 enables
Add test for DCE of printf and stop

(#1067) Faster reg constprop

(#1068) Infer reset

(#1069) Remove redundant code

(#1071) LowerTypesSpec: additional unit test

(#1072) Remove unnecessary 'FIRRTLParser' prefix

(#1074) Use scalafix to remove unused import and deprecated procedure syntax

(#1075) Change Memory Depth to a BigInt

(#1076) Use UnknownKind instead misrepresented NodeKind

(#1079) Dependency API
Make Transform extend TransformLike
Add PhaseManager tests
Add DependencyManager and PhaseManager
Add PreservesAll stackable trait for DependencyAPI
Add a DependencyAPI to firrtl.options.Phase
Add seeded topological sort to DiGraph

(#1081) Update NoCircuitDedupAnnotation so it's available from firrtl.stage.FirrtlMain

(#1082) Bugfix: GroupComponents

(#1085) spec: mixed-input arguments for prim ops are no longer allowed

(#1087) Emit legal Verilog literals for ExtModule IntParams > 32-bit

(#1089) Analog attach order
make analog attachment order fixed with linked hash map

(#1093) Fix typo.

(#1094) Fix bad FirrtlStage deprecation warning

(#1095) Remove unused variables

(#1101) Fix typo

(#1102) Use pattern match instead of hardcode position

(#1106) Add Test for AddDefaults phase

(#1108) Remove shadow type parameter

(#1109) Implement MultiTargetAnnotation

(#1110) Make sure directory exist before writing

(#1111) Add SimplifyMems transform to lower memories without splitting

(#1113) README.md Patches
Fix custom transform example for Stage/Phase
Add Yosys 0.8 as prerequisite (sbt test needs it)

(#1114) Fix typo

(#1118) Remove some warnings

(#1121) Change Dependency API to Class[_ <: A]
Add type aliases for dependencies

(#1126) Fix RenameMap chaining

(#1129) Allow name of blackbox resource .f file to change from static value

(#1134) Filter out more filename extensions for blackbox source headers

(#1139) Fix "since" deprecation, should be "1.3" not "1.2"
Fix "since" deprecation, should be "1.2" not "1.3"

(#1140) Make write-under-write section for mems in spec

(#1142) io.Source is not closed when used in most common text reading idiom

(#1143) Followup to PR #1142
Followup to PR #1142 - use scala.io.Source instead of io.Source - .toList cleaner way to force stream to be read. - clear old commented out code in ProtoBufSpec
Followup to PR #1142 Fixes a threading bug in where lazy reading of file caused a problem for multithreaded access to the that was read.

(#1144) Fix FileUtils.getLines, add simple FileUtils tests
Add FileUtilsSpec
Iterate 1x in FileUtils.getText, DRY out getText

(#1147) Check mems for legal latencies; ban zero write latency.

(#1148) DRY check chirrtl

(#1150) Improve RemoveReset on Invalid Inits
Add tests on RemoveReset of invalid inits
Improve RemoveReset handling of invalid inits

(#1151) Remove unused CheckHighFormLike.IllegalChirrtlMemException

(#1152) Make "build" the default make target rather than "clean"

(#1156) Bump dependency versions

(#1157) Refactor exceptions to remove stack trace from user errors

(#1158) Programmed Stage Death
Add StageError
Add firrtl.options.ExitCode type hierarchy

(#1160) Remove incorrect short option for --info-mode

(#1163) clean up spacing in inline test

(#1166) Refactor: remove redundancy code