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v1.2.1
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@ucbjrl ucbjrl released this 02 Dec 21:22
v1.2.1
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Fix

(#1202/#1225) Fix handling of read enables for write-first (default) memories in VerilogMemDelays
Add tests for memories with latency >1, toggling enables
Add library for streamlined Verilog execution tests
Add test for #1179: comb-loops from VerilogMemDelays
Fix write-first mem enable handling in VerilogMemDelays

(#1246) Error on nested memory datatypes (bp #1238)

Feature

(#1204) Emit Verilog else-if for Register Updates

(#1208) Enhance CheckCombLoops errors with connection info
Add EdgeData trait to mix in to graphs

(#1223) Revert binary-compatibility breaking changes since 1.2.0 and enforce checking
Set up CI for 1.2.x branch

(#1226) Change findInstancesInHierarchy to return implicit top instance (bp #1216)

(#1236) [Backport #1222] Add spec for Analog type and attach statement

(#1243) Make updated type info available in VerilogMemDelays

(#1248) Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS (bp #1219)

(#1250) Add explicit EOF to top-level parser rule (bp #1217)

(#1251) Add separate Issue and PR templates (bp #1206)

(#1252) Add check for multiple sources for same wiring pin (bp #1191)

(#1253) Move CheckResets after CheckCombLoops (bp #1224)

(#1254) getSimpleName considered harmful (bp #1228)

(#1255) Ignore extmodule instances in Flatten (bp #1218)

(#1256) Try fixing travis binary compatibility check

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