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FIRRTL v1.5.0-RC2

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@jackkoenig jackkoenig released this 21 Dec 18:42

1.5.0-RC2 includes all changes from 1.5.0-RC1 so please see the RC1 release notes.

Feature

  • Add RTLIL Backend. (#2331)
    Adds code generation backend targeting RTLIL IR for use with the Yosys open synthesis tool.
  • Disable random init (#2396)
    optional to remove random initialization code in emitted Verilog.
  • Let firrtl based applications run despite loading unknown annotations (#2387)
    Use command-line option --allow-unrecognized-annotations
  • Improve ANTLR Parser (#2343)
    It now uses substantially less memory on large designs
  • Implement CustomRadixTransform for wave viewers (#2434)
  • Enable memory initialization in synthesis for FPGA targets (#2430)

API Removals

  • Modify and optimize performance of propagate annotations (#2393)
    When a transform deletes an Annotation, a DeletedAnnotation is no longer created. Furthermore, debug-mode logging no longer captures any information about annotation changes between transforms. If any of this behavior is desired, please file an issue to restore it under a debug flag.
  • Remove The WriteEmitted Phase (#2390)
  • Remove firrtl.ExecutionOptionsManager (#2422)
  • Remove firrtl.transforms.BlackBoxSourceHelper.fileListName. (#2426)
  • Remove firrtl.transforms.InferResets.DifferingDriverTypesException (#2425)
  • Remove firrtl.transforms.InlineAcrossCastsTransform. (#2424)
  • Remove firrtl.FIRRTLException (#2421)
  • Remove firrtl.Utils.get_flip and firrtl.Utils.indent (#2420)
  • Remove trait firrtl.util.BackendCompilationUtilities (#2423)
  • Remove firrtl.Driver (#2419)

API Deprecations

  • Deprecate all mutable methods on RenameMap (#2444)
    For constructing RenameMaps, use firrtl.renamemap.MutableRenameMap.

BugFix

  • Fix width of signed addition when input to mux (#2440)
  • Support parsing missing keywords as ids (#2381)
  • smt: correctly serialize array index on read (#2446)
  • BlackBoxSourceHelper: ensure trailing newline in .f file (#2405)
  • Hotfix for Vector Reg Init LegalizeConnects Bug (#2380)
  • TopWiring: filter out unnamed declarations when building source lists (#2376)
  • smt: fix handling of div primitive in formal backend (#2409)
  • transforms.formal: ensure named statements as output (#2367)

Dependency Bumping

  • Update sbt to 1.5.7 (#2443)
  • Update sbt to 1.5.6 (#2441)
  • Update os-lib to 0.8.0 (#2442)
  • Update sbt-scalafmt to 2.4.5 (#2433)
  • Update sbt-scalafix to 0.9.33 (#2431)
  • Update sbt-ci-release to 1.5.10 (#2418)
  • Update scalacheck-1-14, ... to 3.2.1.0 (#1850)
  • Update sbt-ci-release to 1.5.9 (#2364)
  • Update scala-parallel-collections to 1.0.4 (#2377)
  • Update sbt-mima-plugin to 1.0.1 (#2385)
  • Update sbt-protobuf to 0.7.1 (#2378)
  • Update sbt-scalafix to 0.9.32 (#2414)
  • Update sbt-scalafmt to 2.4.4 (#2417)
  • Update commons-text to 1.9 (#1789)
  • Update sbt-assembly to 1.1.0 (#1706)
  • Update scala-library, scala-reflect to 2.12.15 (#2358)
  • Update scala-library, scala-reflect to 2.13.7 (#2401)
  • Update sbt-unidoc to 0.5.0 (#2394)
  • Update json4s-native to 3.6.12 (#2406)
  • Update sbt-scoverage to 1.9.2 (#2402)
  • Update antlr4, antlr4-runtime to 4.9.3 (#2407)

Miscellany

  • [spec] Fix formatting of example of memory port types. (#2368)
  • Have Flatten & InlineInstances remove their annotations (#2374)
  • Update spec on extmodule with defname, parameter (#2413)