build(deps): bump third_party/cores/opentitan from eec48c4
to 7704c7a
#6827
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Bumps third_party/cores/opentitan from
eec48c4
to7704c7a
.Commits
7704c7a
[hw,tlul_adapter_sram_racl,rtl] Add RACL protected SRAM adapter6356853
[hw,tlul_adapter_reg_racl,rtl] Implement shim in front of adapterd151e80
[hw,tlul loopback,rtl] Add paramter to control error response75077dd
[hw,clkmgr,rtl] Properly size the measurement counter87feba0
[RACL] Create TLUL user vector based on a role ctn uidd0601d1
[dv, aon_timer] scoreboard model and checks refactorac37212
[dv, aon_timer] Adding CDC-aware intr_state register1fb4d01
[dv, aon_timer] Wait for writes to cross the CDC boundary16a6d85
[dv, aon_timer] Enabling the prediction mask for cip_scb comparisond5d5ccb
[dv, aon_timer] Add convenience functions to cfg object for reuseDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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