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[ipemu] gate dpi call with !reset to work around verilator scheduling…
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… bug
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sequencer committed Jul 29, 2024
1 parent 331a34f commit 252e48a
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion ipemu/src/TestBench.scala
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
val issue = WireDefault(0.U.asTypeOf(new Issue))
val fence = RegInit(false.B)
val outstanding = RegInit(0.U(4.W))
val doIssue: Bool = dut.io.issue.ready && !fence
val doIssue: Bool = dut.io.issue.ready && !fence && !reset
outstanding := outstanding + (doIssue && (issue.meta === 1.U)) - dut.io.issue.valid
// used to gate Xprop when DPI hasn't issued yet.
val didIssue = RegNext(doIssue || didIssue, false.B)
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