fixup

chipsalliance · Jul 25, 2024 · 38e40fe · 38e40fe
1 parent 94cdc3f
commit 38e40fe
Showing 1 changed file with 8 additions and 4 deletions.
diff --git a/rocketv/src/RocketCore.scala b/rocketv/src/RocketCore.scala
@@ -1344,7 +1344,6 @@ class Rocket(val parameter: RocketParameter)
       t1IssueQueue.io.enq.bits.rs2Data := wbRegRS2
       t1.issue.valid := t1IssueQueue.io.deq.valid
       t1.issue.bits := t1IssueQueue.io.deq.bits
-      // TODO: really maintain 3 retire queues? we need to reduce it via a scoreboard.
       val t1MemoryRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.mem.bits), maxCount))
       val t1CSRRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.csr.bits), maxCount))
       val t1XRDRetireQueue = Module(new Queue(chiselTypeOf(t1.retire.rd.bits), maxCount))
@@ -1364,9 +1363,14 @@ class Rocket(val parameter: RocketParameter)
         (empty, full)
       }
       // T1 Memory Scoreboard
-      val lsuGrant:   Bool = t1.issue.valid && wbRegDecodeOutput(parameter.decoderParameter.vectorLSU)
-      val lsuRelease: Bool = t1.retire.mem.fire
-      val (lsuEmpty, _) = counterManagement(countWidth)(lsuGrant, lsuRelease)
+      val t1MemoryGrant:   Bool = t1.issue.valid && wbRegDecodeOutput(parameter.decoderParameter.vectorLSU)
+      val t1MemoryRelease: Bool = t1.retire.mem.fire
+      val (lsuEmpty, _) = counterManagement(countWidth)(t1MemoryGrant, t1MemoryRelease)
+      // T1 CSR Scoreboard
+      val t1CSRGrant:   Bool = t1.issue.valid && wbRegDecodeOutput(???)
+      val t1CSRRelease: Bool = t1.retire.mem.fire
+      // T1 XRD Scoreboard?
+
       // Maintain vector counter
       // There may be 4 instructions in the pipe
       val (vectorEmpty, vectorFull) = counterManagement(countWidth, 4)(t1.issue.valid, ???)