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[rocketemu] refactor AXI read functions and remove the read alignment
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Clo91eaf authored and sequencer committed Jul 24, 2024
1 parent 77210bf commit 4401ddf
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Showing 2 changed files with 16 additions and 44 deletions.
18 changes: 9 additions & 9 deletions rocketemu/driver/src/dpi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -91,7 +91,7 @@ unsafe extern "C" fn axi_write_loadStoreAXI_rs(
payload: *const SvBitVecVal,
) {
debug!(
"axi_write_loadStore (channel_id={channel_id}, awid={awid}, awaddr={awaddr:#x}, \
"axi_write_loadStoreAXI (channel_id={channel_id}, awid={awid}, awaddr={awaddr:#x}, \
awlen={awlen}, awsize=2^{awsize}, awburst={awburst}, awlock={awlock}, awcache={awcache}, \
awprot={awprot}, awqos={awqos}, awregion={awregion})"
);
Expand All @@ -118,12 +118,12 @@ unsafe extern "C" fn axi_read_loadStoreAXI_rs(
payload: *mut SvBitVecVal,
) {
debug!(
"axi_read_highBandwidth (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
"axi_read_loadStoreAXI (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
arlen={arlen}, arsize={arsize}, arburst={arburst}, arlock={arlock}, arcache={arcache}, \
arprot={arprot}, arqos={arqos}, arregion={arregion})"
);
let sim = &mut *(target as *mut Simulator);
let response = sim.axi_read_load_store(araddr as u32, arsize as u64);
let response = sim.axi_read(araddr as u32, arsize as u64);
fill_axi_read_payload(payload, sim.dlen, &response.data);
}

Expand All @@ -144,21 +144,21 @@ unsafe extern "C" fn axi_read_instructionFetchAXI_rs(
payload: *mut SvBitVecVal,
) {
debug!(
"axi_read_indexed (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
"axi_read_instructionFetchAXI (channel_id={channel_id}, arid={arid}, araddr={araddr:#x}, \
arlen={arlen}, arsize={arsize}, arburst={arburst}, arlock={arlock}, arcache={arcache}, \
arprot={arprot}, arqos={arqos}, arregion={arregion})"
);
let driver = &mut *(target as *mut Simulator);
let response = driver.axi_read_instruction(araddr as u32, arsize as u64);
fill_axi_read_payload(payload, driver.dlen, &response.data);
let sim = &mut *(target as *mut Simulator);
let response = sim.axi_read(araddr as u32, arsize as u64);
fill_axi_read_payload(payload, sim.dlen, &response.data);
}

#[no_mangle]
unsafe extern "C" fn cosim_init_rs(call_init: *mut SvBit) -> *mut () {
let args = SimulationArgs::parse();
*call_init = 1;
let driver = Box::new(Simulator::new(args));
Box::into_raw(driver) as *mut ()
let sim = Box::new(Simulator::new(args));
Box::into_raw(sim) as *mut ()
}

#[no_mangle]
Expand Down
42 changes: 7 additions & 35 deletions rocketemu/driver/src/sim.rs
Original file line number Diff line number Diff line change
Expand Up @@ -260,48 +260,20 @@ impl Simulator {
self.write_mem(addr, self.dlen / 8, strobe, data);
}

fn read_mem(&mut self, addr: u32, size: u32, alignment_bytes: u32) -> Vec<u8> {
fn read_mem(&mut self, addr: u32, size: u32) -> Vec<u8> {
assert!(
addr % size == 0 || addr % alignment_bytes == 0,
"unaligned access addr={addr} size={size}bytes dlen={alignment_bytes}bytes"
addr % size == 0,
"unaligned access addr={addr} size={size}bytes"
);
let residue_addr = addr % alignment_bytes;
let aligned_addr = addr - residue_addr;
if size < alignment_bytes {
// narrow
(0..alignment_bytes)
.map(|i| {
let i_addr = aligned_addr + i;
if addr <= i_addr && i_addr < addr + size {
self.mem[i_addr as usize]
} else {
0
}
})
.collect()
} else {
// normal
(0..size).map(|i| self.mem[(addr + i) as usize]).collect()
}
}

pub fn axi_read_instruction(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
let size = 1 << arsize; // size in bytes
let data = self.read_mem(addr, size, 4);
let data_hex = hex::encode(&data);
info!(
"[{}] axi_read_indexed (addr={addr:#x}, size={size}, data={data_hex})",
0
);
AxiReadPayload { data }
(0..size).map(|i| self.mem[(addr + i) as usize]).collect()
}

pub(crate) fn axi_read_load_store(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
pub fn axi_read(&mut self, addr: u32, arsize: u64) -> AxiReadPayload {
let size = 1 << arsize; // size in bytes
let data = self.read_mem(addr, size, self.dlen / 8);
let data = self.read_mem(addr, size);
let data_hex = hex::encode(&data);
info!(
"[{}] axi_read_high_bandwidth (addr={addr:#x}, size={size}, data={data_hex})",
"[{}] axi_read (addr={addr:#x}, size={size}, data={data_hex})",
0
);
AxiReadPayload { data }
Expand Down

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