Skip to content

Commit

Permalink
[rockett1] draft Testbench
Browse files Browse the repository at this point in the history
  • Loading branch information
sequencer committed Aug 3, 2024
1 parent ef8e2df commit 4a3cfe7
Show file tree
Hide file tree
Showing 2 changed files with 87 additions and 0 deletions.
11 changes: 11 additions & 0 deletions elaborator/src/Main.scala
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ import mainargs._
import org.chipsalliance.t1.rtl.T1Parameter
import org.chipsalliance.rocketv.RocketTileParameter
import chisel3.panamalib.option._
import org.chipsalliance.t1.tile.T1RocketTileParameter

object Main {
implicit object PathRead extends TokensReader.Simple[os.Path] {
Expand Down Expand Up @@ -74,6 +75,13 @@ object Main {
def parameter: RocketTileParameter = generator.parameter
}

case class T1RocketConfig(
@arg(name = "t1rocket-config", short = 'c') rocketConfig: os.Path) {
def generator = upickle.default
.read[chisel3.experimental.SerializableModuleGenerator[org.chipsalliance.t1.tile.T1RocketTile, org.chipsalliance.t1.tile.T1RocketTileParameter]](ujson.read(os.read(rocketConfig)))
def parameter: T1RocketTileParameter = generator.parameter
}

implicit def ipConfig: ParserForClass[IPConfig] = ParserForClass[IPConfig]
implicit def rocketConfig: ParserForClass[RocketConfig] = ParserForClass[RocketConfig]

Expand All @@ -87,6 +95,9 @@ object Main {
@main def rocketemu(elaborateConfig: ElaborateConfig, rocketConfig: RocketConfig): Unit = elaborateConfig.elaborate(() =>
new org.chipsalliance.t1.rocketv.TestBench(rocketConfig.generator)
)
@main def t1rocketemu(elaborateConfig: ElaborateConfig, t1rocketConfig: T1RocketConfig): Unit = elaborateConfig.elaborate(() =>
new org.chipsalliance.t1.t1rocketemu.TestBench(t1rocketConfig.generator)
)
// format: on

def main(args: Array[String]): Unit = ParserForMethods(this).runOrExit(args)
Expand Down
76 changes: 76 additions & 0 deletions t1rocketemu/src/TestBench.scala
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
// SPDX-License-Identifier: Apache-2.0
// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>

package org.chipsalliance.t1.t1rocketemu

import chisel3.experimental.{BaseModule, ExtModule, SerializableModuleGenerator}
import chisel3.util.HasExtModuleInline
import chisel3.{Bool, ImplicitClock, ImplicitReset, Module, Output, RawModule}
import org.chipsalliance.t1.tile.{T1RocketTile, T1RocketTileParameter}

class TestBench(generator: SerializableModuleGenerator[T1RocketTile, T1RocketTileParameter])
extends RawModule
with ImplicitClock
with ImplicitReset {
val clockGen = Module(new ExtModule with HasExtModuleInline {

override def desiredName = "ClockGen"
setInline(
s"$desiredName.sv",
s"""module $desiredName(output reg clock, output reg reset);
| export "DPI-C" function dump_wave;
| function dump_wave(input string file);
|`ifdef VCS
| $$fsdbDumpfile(file);
| $$fsdbDumpvars("+all");
| $$fsdbDumpon;
|`endif
|`ifdef VERILATOR
| $$dumpfile(file);
| $$dumpvars(0);
|`endif
| endfunction;
|
| import "DPI-C" context function void t1_cosim_init();
| initial begin
| t1_cosim_init();
| clock = 1'b0;
| reset = 1'b1;
| end
| initial #(11) reset = 1'b0;
| always #10 clock = ~clock;
|endmodule
|""".stripMargin
)
val clock = IO(Output(Bool()))
val reset = IO(Output(Bool()))
})
def clock = clockGen.clock.asClock
def reset = clockGen.reset
override def implicitClock = clockGen.clock.asClock
override def implicitReset = clockGen.reset
val dut: T1RocketTile with BaseModule = Module(generator.module())
dut.io.clock := clock
dut.io.reset := reset
dut.io.hartid
dut.io.resetVector
dut.io.debug
dut.io.mtip
dut.io.msip
dut.io.meip
dut.io.seip
dut.io.lip
dut.io.nmi
dut.io.nmiInterruptVector
dut.io.nmiIxceptionVector
dut.io.buserror
dut.io.wfi
dut.io.halt
dut.io.instructionFetchAXI
dut.io.itimAXI
dut.io.loadStoreAXI
dut.io.dtimAXI
dut.io.dtimAXI
dut.io.highBandwidthAXI
dut.io.highOutstandingAXI
}

0 comments on commit 4a3cfe7

Please sign in to comment.