use sew

chipsalliance · Aug 2, 2024 · 68e1dda · 68e1dda
1 parent 3b4882e
commit 68e1dda
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Showing 8 changed files with 105 additions and 20 deletions.
diff --git a/t1/src/LaneZvbb.scala b/t1/src/LaneZvbb.scala
@@ -22,8 +22,9 @@ case class LaneZvbbParam(datapathWidth: Int, latency: Int) extends VFUParameter
 }
 
 class LaneZvbbRequest(datapathWidth: Int) extends VFUPipeBundle {
-  val src   = Vec(3, UInt(datapathWidth.W))
+  val src    = Vec(3, UInt(datapathWidth.W))
   val opcode = UInt(4.W)
+  val vSew   = UInt(2.W)
 }
 
 class LaneZvbbResponse(datapathWidth: Int)  extends VFUPipeBundle {
@@ -37,21 +38,98 @@ class LaneZvbb(val parameter: LaneZvbbParam)
   val response: LaneZvbbResponse = Wire(new LaneZvbbResponse(parameter.datapathWidth))
   val request : LaneZvbbRequest  = connectIO(response).asTypeOf(parameter.inputBundle)
 
-  val zvbbSrc: UInt = request.src(1) // vs1 or rs1
-  val zvbbRs: UInt = request.src(0) // vs2
+  val zvbbSrc: UInt = request.src(1) // vs2
+  val zvbbRs:  UInt = request.src(0) // vs1 or rs1
+  val vSew:    UInt = UIntToOH(request.vSew) // sew = 0, 1, 2
 
-  val zvbbBRev  = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.reverse).asUInt // element's bit reverse
-  val zvbbBRev8 = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.grouped(8).map(s => VecInit(s.reverse)).toSeq).asUInt // byte's bit reverse
-  val zvbbRev8  = VecInit(zvbbSrc(parameter.datapathWidth-1, 0).asBools.grouped(8).map(s => VecInit(s)).toSeq.reverse).asUInt // element's byte reverse
+  val zvbbBRev  = VecInit(zvbbSrc.asBools.reverse).asUInt // element's bit reverse
+  val zvbbBRev8 = VecInit(zvbbSrc.asBools.grouped(8).map(s => VecInit(s.reverse)).toSeq).asUInt // byte's bit reverse
+  val zvbbRev8  = VecInit(zvbbSrc.asBools.grouped(8).map(s => VecInit(s)).toSeq.reverse).asUInt // element's byte reverse
 
-  val zvbbCLZ = (PopCount(scanLeftOr(zvbbBRev)) - 1.U).asUInt
-  val zvbbCTZ = (PopCount(scanRightOr(zvbbBRev)) - 1.U).asUInt
-  val zvbbROL = zvbbSrc.rotateLeft(zvbbRs(4, 0)).asUInt
-  val zvbbROR = zvbbSrc.rotateRight(zvbbRs(4, 0)).asUInt
+  val zvbbSrc16a = zvbbSrc(parameter.datapathWidth-1, parameter.datapathWidth-16)
+  val zvbbSrc16b = zvbbSrc(parameter.datapathWidth-17, parameter.datapathWidth-32)
+  val zvbbSrc8a = zvbbSrc(parameter.datapathWidth-1, parameter.datapathWidth-8)
+  val zvbbSrc8b = zvbbSrc(parameter.datapathWidth-9, parameter.datapathWidth-16)
+  val zvbbSrc8c = zvbbSrc(parameter.datapathWidth-17, parameter.datapathWidth-24)
+  val zvbbSrc8d = zvbbSrc(parameter.datapathWidth-25, parameter.datapathWidth-32)
 
-  val zvbbSLL64 = (0.U((parameter.datapathWidth).W) ## zvbbSrc(parameter.datapathWidth-1, 0)).asUInt << zvbbRs(5, 0)
+  val zvbbRs16a = zvbbRs(parameter.datapathWidth-1, parameter.datapathWidth-16)
+  val zvbbRs16b = zvbbRs(parameter.datapathWidth-17, parameter.datapathWidth-32)
+  val zvbbRs8a = zvbbRs(parameter.datapathWidth-1, parameter.datapathWidth-8)
+  val zvbbRs8b = zvbbRs(parameter.datapathWidth-9, parameter.datapathWidth-16)
+  val zvbbRs8c = zvbbRs(parameter.datapathWidth-17, parameter.datapathWidth-24)
+  val zvbbRs8d = zvbbRs(parameter.datapathWidth-25, parameter.datapathWidth-32)
+
+  val zvbbCLZ32 = (32.U - PopCount(scanRightOr(zvbbSrc))).asUInt
+  val zero10 = Fill(11, 0.U)
+  val zvbbCLZ16 = zero10 ## (16.U - PopCount(scanRightOr(zvbbSrc16a))).asUInt(4, 0) ##
+                  zero10 ## (16.U - PopCount(scanRightOr(zvbbSrc16b))).asUInt(4, 0)
+  val zero3 = Fill(4, 0.U)
+  val zvbbCLZ8 = zero3 ## (8.U - PopCount(scanRightOr(zvbbSrc8a))).asUInt(3, 0) ##
+                 zero3 ## (8.U - PopCount(scanRightOr(zvbbSrc8b))).asUInt(3, 0) ##
+                 zero3 ## (8.U - PopCount(scanRightOr(zvbbSrc8c))).asUInt(3, 0) ##
+                 zero3 ## (8.U - PopCount(scanRightOr(zvbbSrc8d))).asUInt(3, 0)
+  val zvbbCLZ = Mux1H(vSew, Seq(
+    zvbbCLZ8,
+    zvbbCLZ16,
+    zvbbCLZ32,
+  ))
+
+  val zvbbCTZ32 = (32.U - PopCount(scanLeftOr(zvbbSrc))).asUInt
+  val zvbbCTZ16 = zero10 ## (16.U - PopCount(scanLeftOr(zvbbSrc16a))).asUInt(4, 0) ##
+                  zero10 ## (16.U - PopCount(scanLeftOr(zvbbSrc16b))).asUInt(4, 0)
+  val zvbbCTZ8 = zero3 ## (8.U - PopCount(scanLeftOr(zvbbSrc8a))).asUInt(3, 0) ##
+                 zero3 ## (8.U - PopCount(scanLeftOr(zvbbSrc8b))).asUInt(3, 0) ##
+                 zero3 ## (8.U - PopCount(scanLeftOr(zvbbSrc8c))).asUInt(3, 0) ##
+                 zero3 ## (8.U - PopCount(scanLeftOr(zvbbSrc8d))).asUInt(3, 0)
+  val zvbbCTZ = Mux1H(vSew, Seq(
+    zvbbCTZ8,
+    zvbbCTZ16,
+    zvbbCTZ32,
+  ))
+
+  val zvbbROL32 = zvbbSrc.rotateLeft(zvbbRs(4, 0)).asUInt
+  val zvbbROL16 = zvbbSrc16a.rotateLeft(zvbbRs16a(3, 0)).asUInt(15, 0) ##
+                  zvbbSrc16b.rotateLeft(zvbbRs16b(3, 0)).asUInt(15, 0)
+  val zvbbROL8 = zvbbSrc8a.rotateLeft(zvbbRs8a(2, 0)).asUInt(7, 0) ##
+                 zvbbSrc8b.rotateLeft(zvbbRs8b(2, 0)).asUInt(7, 0) ##
+                 zvbbSrc8c.rotateLeft(zvbbRs8c(2, 0)).asUInt(7, 0) ##
+                 zvbbSrc8d.rotateLeft(zvbbRs8d(2, 0)).asUInt(7, 0)
+  val zvbbROL = Mux1H(vSew, Seq(
+    zvbbROL8,
+    zvbbROL16,
+    zvbbROL32,
+  ))
+
+  val zvbbROR32 = zvbbSrc.rotateRight(zvbbRs(4, 0)).asUInt
+  val zvbbROR16 = zvbbSrc16a.rotateRight(zvbbRs16a(3, 0)).asUInt(15, 0) ##
+                  zvbbSrc16b.rotateRight(zvbbRs16b(3, 0)).asUInt(15, 0)
+  val zvbbROR8 = zvbbSrc8a.rotateRight(zvbbRs8a(2, 0)).asUInt(7, 0) ##
+                 zvbbSrc8b.rotateRight(zvbbRs8b(2, 0)).asUInt(7, 0) ##
+                 zvbbSrc8c.rotateRight(zvbbRs8c(2, 0)).asUInt(7, 0) ##
+                 zvbbSrc8d.rotateRight(zvbbRs8d(2, 0)).asUInt(7, 0)
+  val zvbbROR = Mux1H(vSew, Seq(
+    zvbbROR8,
+    zvbbROR16,
+    zvbbROR32,
+  ))
+
+  val zvbbSLL64_32 = (0.U((parameter.datapathWidth).W) ## zvbbSrc).asUInt << zvbbRs(5, 0)
+  val zvbbSLL64_16 = ((0.U(16.W) ## zvbbSrc16a).asUInt << zvbbRs16a(4, 0)).asUInt(31, 0) ##
+                     ((0.U(16.W) ## zvbbSrc16b).asUInt << zvbbRs16b(4, 0)).asUInt(31, 0)
+  val zvbbSLL64_8 = ((0.U(8.W) ## zvbbSrc8a).asUInt << zvbbRs8a(3, 0)).asUInt(15, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8b).asUInt << zvbbRs8b(3, 0)).asUInt(15, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8c).asUInt << zvbbRs8c(3, 0)).asUInt(15, 0) ##
+                    ((0.U(8.W) ## zvbbSrc8d).asUInt << zvbbRs8d(3, 0)).asUInt(15, 0)
+  val zvbbSLL64 = Mux1H(vSew, Seq(
+    zvbbSLL64_8,
+    zvbbSLL64_16,
+    zvbbSLL64_32,
+  ))
   val zvbbSLL = zvbbSLL64(parameter.datapathWidth-1, 0)
   val zvbbSLLMSB = zvbbSLL64(2*parameter.datapathWidth-1, parameter.datapathWidth)
+
+  val zvbbANDN = zvbbSrc & (~zvbbRs)
 
   response.data := Mux1H(UIntToOH(request.opcode), Seq(
       zvbbBRev,
@@ -62,6 +140,7 @@ class LaneZvbb(val parameter: LaneZvbbParam)
       zvbbROL,
       zvbbROR,
       zvbbSLL,
+      zvbbANDN,
     )
   )
   response.source2 := Mux(request.opcode === 7.U, zvbbSLLMSB, 0.U)

diff --git a/t1/src/decoder/Decoder.scala b/t1/src/decoder/Decoder.scala
@@ -342,6 +342,7 @@ object Decoder {
           case _: zvbbUop5.type => BitPat("b0101")
           case _: zvbbUop6.type => BitPat("b0110")
           case _: zvbbUop7.type => BitPat("b0111")
+          case _: zvbbUop8.type => BitPat("b1000")
           case _ => BitPat.dontCare(4)
         }
       case _ => BitPat.dontCare(4)

diff --git a/t1/src/decoder/attribute/isItype.scala b/t1/src/decoder/attribute/isItype.scala
@@ -51,6 +51,9 @@ object isItype {
       "vssra.vi",
       "vssrl.vi",
       "vxor.vi",
+      // rv_zvbb
+      "vror.vi",
+      "vwsll.vi",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isLogic.scala b/t1/src/decoder/attribute/isLogic.scala
@@ -37,9 +37,6 @@ object isLogic {
       "vxor.vi",
       "vxor.vv",
       "vxor.vx",
-      // rv_zvbb
-      "vandn.vv",
-      "vandn.vx",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isMasklogic.scala b/t1/src/decoder/attribute/isMasklogic.scala
@@ -31,9 +31,6 @@ object isMasklogic {
       "vmsof.m",
       "vmxnor.mm",
       "vmxor.mm",
-      // rv_zvbb
-      "vandn.vv",
-      "vandn.vx",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/isZvbb.scala b/t1/src/decoder/attribute/isZvbb.scala
@@ -17,6 +17,8 @@ object isZvbb {
 
   def y(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched = if(t1DecodePattern.param.zvbbEnable) Seq(
+      "vandn.vv",
+      "vandn.vx",
       "vbrev.v",
       "vbrev8.v",
       "vrev8.v",

diff --git a/t1/src/decoder/attribute/logicUop.scala b/t1/src/decoder/attribute/logicUop.scala
@@ -81,9 +81,6 @@ object LogicUop {
   def t8(t1DecodePattern: T1DecodePattern): Boolean = {
     val allMatched: Seq[String] = Seq(
       "vmnand.mm",
-      // rv_zvbb
-      "vandn.vv",
-      "vandn.vx",
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }

diff --git a/t1/src/decoder/attribute/zvbbUop.scala b/t1/src/decoder/attribute/zvbbUop.scala
@@ -14,6 +14,7 @@ object zvbbUop4 extends ZvbbUOPType
 object zvbbUop5 extends ZvbbUOPType
 object zvbbUop6 extends ZvbbUOPType
 object zvbbUop7 extends ZvbbUOPType
+object zvbbUop8 extends ZvbbUOPType
 
 object ZvbbUOP {
   def apply(t1DecodePattern: T1DecodePattern): Uop = {
@@ -26,6 +27,7 @@ object ZvbbUOP {
       t5 _ -> zvbbUop5,
       t6 _ -> zvbbUop6,
       t7 _ -> zvbbUop7,
+      t8 _ -> zvbbUop8,
     ).collectFirst {
       case (fn, tpe) if fn(t1DecodePattern) => tpe
     }.getOrElse(UopDC)
@@ -83,4 +85,11 @@ object ZvbbUOP {
     )
     allMatched.contains(t1DecodePattern.instruction.name)
   }
+  def t8(t1DecodePattern: T1DecodePattern): Boolean = {
+    val allMatched: Seq[String] = Seq(
+      "vandn.vv",
+      "vandn.vx",
+    )
+    allMatched.contains(t1DecodePattern.instruction.name)
+  }
 }