[rtl] start address in store unit need wait for axi write confirm.

chipsalliance · Jul 16, 2024 · b6f30e5 · b6f30e5
1 parent 444f05f
commit b6f30e5
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Showing 2 changed files with 19 additions and 11 deletions.
diff --git a/t1/src/lsu/LSU.scala b/t1/src/lsu/LSU.scala
@@ -381,6 +381,7 @@ class LSU(param: LSUParameter) extends Module {
 
   // todo: add write token ?
   axi4Port.b.ready := true.B
+  storeUnit.storeResponse := axi4Port.b.valid
   simpleAccessPorts.b.ready := true.B
 
   // other unit <> axi
@@ -436,15 +437,13 @@ class LSU(param: LSUParameter) extends Module {
   storeUnit.vrfReadyToStore := vrfReadyToStore
 
   val unitOrder: Bool = instIndexLE(loadUnit.status.instructionIndex, storeUnit.status.instructionIndex)
-  val storeStartLargerThanLoadStart: Bool = loadUnit.status.startAddress <= storeUnit.status.startAddress
-  val storeStartLessThanLoadEnd: Bool = storeUnit.status.startAddress <= loadUnit.status.endAddress
-  val storeEndLargerThanLoadStart: Bool = loadUnit.status.startAddress <= storeUnit.status.endAddress
-  val storeEndLessThanLoadEnd: Bool = storeUnit.status.endAddress <= loadUnit.status.endAddress
-
-  val addressOverlap: Bool = ((storeStartLargerThanLoadStart && storeStartLessThanLoadEnd) ||
-    (storeEndLargerThanLoadStart && storeEndLessThanLoadEnd))
-  val stallLoad: Bool = !unitOrder && addressOverlap && !storeUnit.status.idle
-  val stallStore: Bool = unitOrder && addressOverlap && !loadUnit.status.idle
+  val loadAddressConflict: Bool = (loadUnit.status.startAddress >= storeUnit.status.startAddress) &&
+    (loadUnit.status.startAddress <= storeUnit.status.endAddress)
+  val storeAddressConflict: Bool = (storeUnit.status.startAddress >= loadUnit.status.startAddress) &&
+    (storeUnit.status.startAddress <= loadUnit.status.endAddress)
+
+  val stallLoad: Bool = !unitOrder && loadAddressConflict && !storeUnit.status.idle
+  val stallStore: Bool = unitOrder && storeAddressConflict && !loadUnit.status.idle
 
   loadUnit.addressConflict := stallLoad
   storeUnit.addressConflict := stallStore

diff --git a/t1/src/lsu/StoreUnit.scala b/t1/src/lsu/StoreUnit.scala
@@ -42,6 +42,8 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
   val vrfReadResults: Vec[UInt] = IO(Input(Vec(param.laneNumber, UInt(param.datapathWidth.W))))
   @public
   val vrfReadyToStore: Bool = IO(Input(Bool()))
+  @public
+  val storeResponse = IO(Input(Bool()))
 
   // store unit probe
   @public
@@ -254,12 +256,19 @@ class StoreUnit(param: MSHRParam) extends StrideBase(param) with LSUPublic {
     0.U(param.cacheLineBits.W)
   memRequest.bits.address := alignedDequeueAddress
 
-  status.idle := !bufferValid && !readStageValid && readQueueClear && !bufferFull
+  val addressQueueSize: Int = (param.vLen * 8) / (param.datapathWidth * param.laneNumber) + 1
+  // address Wait For Response
+  val addressQueue: Queue[UInt] = Module(new Queue[UInt](UInt(param.paWidth.W), addressQueueSize))
+  addressQueue.io.enq.valid := memRequest.fire
+  addressQueue.io.enq.bits := alignedDequeueAddress
+  addressQueue.io.deq.ready := storeResponse
+
+  status.idle := !bufferValid && !readStageValid && readQueueClear && !bufferFull && !addressQueue.io.deq.valid
   val idleNext: Bool = RegNext(status.idle, true.B)
   status.last := (!idleNext && status.idle) || invalidInstructionNext
   status.changeMaskGroup := maskSelect.valid && !lsuRequest.valid
   status.instructionIndex := lsuRequestReg.instructionIndex
-  status.startAddress := alignedDequeueAddress
+  status.startAddress := Mux(addressQueue.io.deq.valid, addressQueue.io.deq.bits, alignedDequeueAddress)
   status.endAddress := ((lsuRequestReg.rs1Data >> param.cacheLineBits).asUInt + cacheLineNumberReg) ##
     0.U(param.cacheLineBits.W)
   dontTouch(status)