[rtl] fix uncertain state(wip).

t1/src/laneStage/ReadStageRRArbiter.scala

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: Apache-2.0
+// SPDX-FileCopyrightText: 2022 Jiuyang Liu <[email protected]>
+
+package org.chipsalliance.t1.rtl.lane
+
+import chisel3._
+import chisel3.util.{Decoupled, Mux1H}
+
+class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
+  val in = Flipped(Vec(n, Decoupled(gen)))
+  val out = Decoupled(gen)
+}
+
+class ReadStageRRArbiter[T <: Data](val gen: T, val n: Int) extends Module {
+  require(n<=2, "Only 2 were needed, so only 2 were made.")
+  val io = IO(new ArbiterIO(gen, n))
+  if (n == 2) {
+    // Choose the first one first
+    val choseMask = RegInit(true.B)
+    val select: Vec[Bool] = VecInit(Seq(
+      io.in.head.valid && (choseMask || !io.in.last.valid),
+      io.in.last.valid && (!choseMask || !io.in.head.valid)
+    ))
+    io.out.valid := io.in.map(_.valid).reduce(_ || _)
+    io.out.bits := Mux1H(select, io.in.map(_.bits))
+    io.in.zip(select).foreach {case (in, s) =>
+      in.ready := s && io.out.ready
+    }
+  } else {
+    io.out <> io.in.head
+  }
+}

t1/src/laneStage/VrfReadPipe.scala

@@ -40,7 +40,7 @@ class VrfReadPipe(parameter: LaneParameter, arbitrate: Boolean = false) extends
     Option.when(arbitrate)(IO(Decoupled(UInt(parameter.datapathWidth.W))))
 
   // arbitrate
-  val reqArbitrate = Module(new RRArbiter(enqEntryType, if(arbitrate) 2 else 1))
+  val reqArbitrate = Module(new ReadStageRRArbiter(enqEntryType, if(arbitrate) 2 else 1))
 
   (Seq(enqueue) ++ contender).zip(reqArbitrate.io.in).zip(Seq(dequeue) ++ contenderDequeue).foreach {
     case ((source, sink), deq) =>

t1/src/vrf/VRF.scala

@@ -329,7 +329,11 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
       bankReadF(i) := bankCorrect & (~o)
       bankReadS(i) := bankCorrect & (~t) & o
       val pipeFirstUsed = Pipe(true.B, firstUsed, parameter.vrfReadLatency).bits
-      readResults(i) := Mux(pipeFirstUsed, Mux1H(pipeBank, readResultS), Mux1H(pipeBank, readResultF))
+      val pipeFire = Pipe(true.B, v.fire, parameter.vrfReadLatency).bits
+      readResults(i) := Mux1H(Seq(
+        (!pipeFirstUsed && pipeFire, Mux1H(pipeBank, readResultF)),
+        (pipeFirstUsed && pipeFire, Mux1H(pipeBank, readResultF)),
+      ))
       (o | bankCorrect, (bankCorrect & o) | t)
   }
   // @todo @Clo91eaf check write port is ready.