[rtl] fix elaborate.

chipsalliance · Oct 23, 2024 · d2c3b28 · d2c3b28
1 parent 06a7344
commit d2c3b28
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Showing 2 changed files with 8 additions and 4 deletions.
diff --git a/t1/src/mask/MaskUnit.scala b/t1/src/mask/MaskUnit.scala
@@ -383,7 +383,9 @@ class MaskUnit(parameter: T1Parameter) extends Module {
   val selectExecuteReq: Seq[ValidIO[MaskUnitReadReq]] = exeReqReg.zipWithIndex.map { case (_, index) =>
     val res: ValidIO[MaskUnitReadReq] = WireInit(0.U.asTypeOf(Valid(new MaskUnitReadReq(parameter))))
     res.bits.vs           := instReg.vs2 + requestStageReadState.vsGrowth(index)
-    res.bits.offset       := requestStageReadState.readOffset(index)
+    if (parameter.laneParam.vrfOffsetBits > 0) {
+      res.bits.offset := requestStageReadState.readOffset(index)
+    }
     res.bits.readLane     := requestStageReadState.accessLane(index)
     res.bits.dataOffset   := cutUIntBySize(requestStageReadState.readDataOffset, parameter.laneNumber)(index)
     res.bits.requestIndex := index.U

diff --git a/t1/src/vrf/VRF.scala b/t1/src/vrf/VRF.scala
@@ -268,8 +268,9 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
   val portFireCount: UInt = PopCount(VecInit(readRequests.map(_.fire) :+ write.fire))
   dontTouch(portFireCount)
 
-  val writeBank: UInt =
-    if (parameter.rfBankNum == 1) true.B else UIntToOH(write.bits.offset(log2Ceil(parameter.rfBankNum) - 1, 0))
+  val writeIndex: UInt = write.bits.vd ## write.bits.offset
+  val writeBank:  UInt =
+    if (parameter.rfBankNum == 1) true.B else UIntToOH(writeIndex(log2Ceil(parameter.rfBankNum) - 1, 0))
 
   // Add one more record slot to prevent there is no free slot when the instruction comes in
   // (the slot will die a few cycles later than the instruction)
@@ -350,8 +351,9 @@ class VRF(val parameter: VRFParam) extends Module with SerializableModule[VRFPar
           .reduce(_ && _) && portConflictCheck
       }
       val validCorrect: Bool         = if (i == (readRequests.size - 1)) v.valid && checkResult.get else v.valid
+      val address             = v.bits.vs ## v.bits.offset
       // select bank
-      val bank                = if (parameter.rfBankNum == 1) true.B else UIntToOH(v.bits.offset(log2Ceil(parameter.rfBankNum) - 1, 0))
+      val bank                = if (parameter.rfBankNum == 1) true.B else UIntToOH(address(log2Ceil(parameter.rfBankNum) - 1, 0))
       val pipeBank            = Pipe(true.B, bank, parameter.vrfReadLatency).bits
       val bankCorrect         = Mux(validCorrect, bank, 0.U(parameter.rfBankNum.W))
       val readPortCheckSelect = parameter.ramType match {