Link Rocket and T1 for RocketT1Tile #684
Closed
Commits on Aug 6, 2024
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Signed-off-by: Avimitin <[email protected]>
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Signed-off-by: Avimitin <[email protected]>
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Signed-off-by: Avimitin <[email protected]>
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[nix] fix codegen compile for zvbb insn
Signed-off-by: Avimitin <[email protected]>
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Commits on Aug 7, 2024
Commits on Aug 8, 2024
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[nix] add standalone LLVM build for buddy-mlir
Signed-off-by: Avimitin <[email protected]>
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[nix] add Python module support for buddy-mlir
Signed-off-by: Avimitin <[email protected]>
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Signed-off-by: Avimitin <[email protected]>
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[pytorch] use file write instead of print
Signed-off-by: Avimitin <[email protected]>
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Signed-off-by: Avimitin <[email protected]>
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[ci] add PyTorch tests into CI
Only add for blastoise cuz the pytorch.demo tests required zve32f.
Commits on Aug 9, 2024
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[rocketv] add elaborator for ALU
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ALU config --xLen 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ALU design --parameter ./ALU.json --run-firtool
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[rocketv] add elaborator for AMOALU
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.AMOALU config --operandBits 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.AMOALU design --parameter ./AMOALU.json --run-firtool
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[rocketv] add elaborator for BreakpointUnit
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BreakpointUnit config --nBreakpoints 4 --xLen 32 --useBPWatch true --vaddrBits 32 --mcontextWidth 0 --scontextWidth 0 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BreakpointUnit design --parameter ./BreakpointUnit.json --run-firtool
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[rocketv] add elaborator for BTB
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BTB config --useAsyncReset true --fetchBytes 16 --vaddrBits 34 --entries 28 --nMatchBits 14 --nPages 6 --nRAS 6 --cacheBlockBytes 64 --iCacheSet 64 --useCompressed true --updatesOutOfOrder false --bht-nEntries 512 --bht-counterLength 1 --bht-historyLength 8 --bht-historyBits 3 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.BTB design --parameter ./BTB.json --run-firtool
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[rocketv] add elaborator for CSR
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.CSR config --vLen 512 --useAsyncReset false --xLen 32 --fLen 32 --usingSupervisor false --usingFPU true --usingUser false --usingVM false --pgLevels 2 --hartIdLen 1 --usingCompressed true --usingAtomics true --usingDebug true --usingMulDiv true --usingVector true - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.CSR design --parameter ./CSR.json --run-firtool
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[rocketv] add elaborator for Decoder
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Decoder config --pipelinedMul false --fenceIFlushDCache false --instructionSets rv32_i --instructionSets rv_v - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Decoder design --parameter ./Decoder.json --run-firtool
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[rocketv] add elaborator for RVCExpander
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RVCExpander config --xLen 32 --usingCompressed true - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RVCExpander design --parameter ./RVCExpander.json --run-firtool
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[rocketv] add elaborator for IBuf
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.IBuf design --useAsyncReset true --xLen 32 --usingCompressed true --vaddrBits 32 --entries 4 --vaddrBitsExtended 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.IBuf design --parameter ./IBuf.json --run-firtool
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[rocketv] add elaborator for MulDiv and PipelinedMultiplier
- MulDiv - generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.MulDiv config --useAsyncReset true --latency 2 --width 32 --divUnroll 1 --divEarlyOut false --divEarlyOutGranularity 1 --mulUnroll 1 --mulEarlyOut false - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.MulDiv design --parameter ./MulDiv.json --run-firtool - PipelinedMultiplier - generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PipelinedMultiplier config --useAsyncReset true --latency 2 --width 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PipelinedMultiplier design --parameter ./PipelinedMultiplier.json --run-firtool
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[rocketv] add elaborator for PMAChecker
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PMAChecker config --paddrBits 32 --legal 00000000-ffffffff --cacheable 80000000-ffffffff --read 00000000-ffffffff --write 00000000-ffffffff --putPartial 00000000-ffffffff --exec 80000000-ffffffff --sideEffects 00000000-3fffffff - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PMAChecker design --parameter ./PMAChecker.json --run-firtool
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[rocketv] add elaborator for PMAChecker
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PMPChecker config --nPMPs 8 --paddrBits 32 --lgMaxSize 4 --pmpGranularity 4 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PMPChecker design --parameter ./PMPChecker.json --run-firtool
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[rocketv] add elaborator for PTW
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PTW config --useAsyncReset false --hasClockGate true --usingVM false --usingHypervisor false --xLen 32 --fLen 32 --paddrBits 32 --asidBits 0 --pgLevels 2 --nPTECacheEntries 8 --nL2TLBWays 1 --nL2TLBEntries 0 --nPMPs 9 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.PTW design --parameter ./PTW.json --run-firtool
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[rocketv] add elaborator for ICache
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ICache config --vaddrBits 32 --paddrBits 32 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.ICache design --parameter ./ICache.json --run-firtool
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[rocketv] add elaborator for FPU
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.FPU config --useAsyncReset true --useClockGating true --xLen 32 --fLen 32 --minFLen 32 --sfmaLatency 3 --dfmaLatency 4 --divSqrt true --hartIdLen 1 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.FPU design --parameter ./FPU.json --run-firtool
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[rocketv] add elaborator for TLB
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.TLB config --useAsyncReset true --xLen 32 --nSets 1 --nWays 32 --nSectors 4 --nSuperpageEntries 4 --asidBits 0 --pgLevels 2 --usingHypervisor false --usingAtomics true --usingDataScratchpad false --usingAtomicsOnlyForIO false --usingVM false --usingAtomicsInCache false --nPMPs 8 --paddrBits 32 --legal 00000000-ffffffff --cacheable 80000000-ffffffff --read 00000000-ffffffff --write 00000000-ffffffff --putPartial 00000000-ffffffff --exec 80000000-ffffffff --sideEffects 00000000-3fffffff --isITLB true - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.TLB design --parameter ./TLB.json --run-firtool
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[rocketv] add elaborator for DCache
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.DCache config --xLen=64 --fLen=64 --vaddrBitsExtended=1 --vaddrBits=64 --paddrBits=64 - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.DCache design --parameter ./DCache.json --run-firtool
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[rocketv] add elaborator for Frontend
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Frontend config --useAsyncReset false --clockGate true --xLen 32 --usingAtomics true --usingDataScratchpad false --usingVM false --usingCompressed true --usingBTB false --itlbNSets 1 --itlbNWays 32 --itlbNSectors 4 --itlbNSuperpageEntries 4 --blockBytes 32 --iCacheNSets 64 --iCacheNWays 4 --iCachePrefetch false --btbEntries 28 --btbNMatchBits 14 --btbUpdatesOutOfOrder false --nPages 6 --nRAS 6 --nPMPs 8 --paddrBits 32 --pgLevels 2 --asidBits 0 --bhtNEntries 512 --bhtCounterLength 1 --bhtHistoryLength 8 --bhtHistoryBits 3 --legal 00000000-ffffffff --cacheable 80000000-ffffffff --read 00000000-ffffffff --write 00000000-ffffffff --putPartial 00000000-ffffffff --exec 80000000-ffffffff --sideEffects 00000000-3fffffff - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Frontend design --parameter ./Frontend.json --run-firtool
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[rocketv] add elaborator for Rocket
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Rocket config --useAsyncReset true --clockGate true --instructionSets rv32_i --vLen 0 --usingUser false --hartIdLen 1 --nPMPs 8 --asidBits 0 --nBreakpoints 1 --usingBTB false --useBPWatch false --mcontextWidth 0 --scontextWidth 0 --mulDivLantency 2 --divUnroll 1 --divEarlyOut false --divEarlyOutGranularity 1 --mulUnroll 1 --mulEarlyOut false --paddrBits 32 --cacheBlockBytes 32 --hasBeu false --fenceIFlushDCache false --fastLoadByte false --fastLoadWord false --dcacheNSets 64 --flushOnFenceI false - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.Rocket design --parameter ./Rocket.json --run-firtool
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[rocketv] add elaborator for RocketTile
- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RocketTile config --useAsyncReset false --clockGate true --instructionSets rv32_i --priv m --hartIdLen 4 --useBPWatch false --mcontextWidth 0 --scontextWidth 0 --asidBits 0 --resetVectorBits 32 --nBreakpoints 0 --dtlbNWays 0 --dtlbNSets 0 --itlbNSets 0 --itlbNWays 0 --itlbNSectors 0 --itlbNSuperpageEntries 0 --nPTECacheEntries 0 --nL2TLBWays 0 --nL2TLBEntries 0 --paddrBits 32 --cacheBlockBytes 32 --nPMPs 8 --legal 00000000-ffffffff --cacheable 80000000-ffffffff --read 00000000-ffffffff --write 00000000-ffffffff --putPartial 00000000-ffffffff --logic 0 --arithmetic 0 --exec 80000000-ffffffff --sideEffects 00000000-3fffffff --btbEntries 28 --btbNMatchBits 14 --btbUpdatesOutOfOrder false --nPages 6 --nRAS 6 --bhtNEntries 512 --bhtCounterLength 1 --bhtHistoryLength 8 --bhtHistoryBits 3 --mulDivLatency 2 --divUnroll 1 --divEarlyOut false --divEarlyOutGranularity 0 --mulUnroll 1 --mulEarlyOut false --sfmaLatency 3 --dfmaLatency 3 --divSqrt true --flushOnFenceI true --fastLoadByte false --fastLoadWord false --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --maxUncachedInFlight 1 --separateUncachedResp false --iCacheNSets 64 --iCacheNWays 4 --iCachePrefetch false - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.rocketv.RocketTile design --parameter ./RocketTile.json --run-firtool
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Commits on Aug 12, 2024
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Add a derivation to get RocketTile.{anno.json,fir,sv}. This derivation will read from a pre-generated RocketTile.json for the elaborator. Signed-off-by: Avimitin <[email protected]> -
This derivation will produced firtool emitted MLIR bytecode. Signed-off-by: Avimitin <[email protected]>
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This derivation contains firtool emitted verilog. Signed-off-by: Avimitin <[email protected]>
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[nix] add new derivation rocketv-verilated-csrc
This derivation will produce headers and lib verilated from verilator. Signed-off-by: Avimitin <[email protected]>
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[rocketemu] implement TestBench for RocketV Emulator
Signed-off-by: Avimitin <[email protected]>
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[nix] add rocketv into elaborator source
Signed-off-by: Avimitin <[email protected]>
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[nix] use elaborator for Rocket generate
Signed-off-by: Avimitin <[email protected]>
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[rocketemu] expose AXI4 agent as C-API
Signed-off-by: Avimitin <[email protected]>
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[nix] add scope for rocketemu attribute
Signed-off-by: Avimitin <[email protected]>
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[rocketemu] implemented rocket driver
Signed-off-by: Avimitin <[email protected]>
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[rocketemu] update TestBench implementation
This commit keep AXI agent implementation in sync with the axi4-t1 branch, with ClockGen and DumpWave module embedded inside the TestBench module. Signed-off-by: Avimitin <[email protected]>
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[rocketemu] update DPI C binding
Signed-off-by: Avimitin <[email protected]>
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[nix] add riscv-tests into overlay
Signed-off-by: Avimitin <[email protected]>
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[doc] add document about rocket emulator
Signed-off-by: Avimitin <[email protected]>
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[rocketemu] migrate AXI from master
Signed-off-by: Avimitin <[email protected]>
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[rocketemu] implement waveform generate
Signed-off-by: Avimitin <[email protected]>
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[rocketemu] add riscv test env
[rocketemu] fix wrong exit macro [rocketemu] fix wrong sw format [nix] use t1-env for riscv-tests [tests] fix MMIO write when exit [rocketemu] remove ecall
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[nix] add difftest derivation for rocketv
Signed-off-by: Avimitin <[email protected]>
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[rocketemu] build rocket offline difftest
[rocketemu] catch watchdog timeout event in offline difftest [rocketemu] optimize difftest loop [rocketemu] should not soft link the nix result directly [rocketemu] spike event record reg write idx with hex [rocketemu] add support for msu priviledge [rocketemu] skip check when spike/rtl reg write idx == 0
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[nix] refactor the rocketv subattr
Signed-off-by: Avimitin <[email protected]>
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[nix] rename default config to "meowth"
Signed-off-by: Avimitin <[email protected]>
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- generate parameter json: mill elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile config --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w - generate verilog: mill elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile design --parameter ./T1RocketTile.json --run-firtool
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nix develop ".#t1.elaborator.editable" -c mill -i elaborator.runMain org.chipsalliance.t1.elaborator.t1rocketv.T1RocketTile config --instructionSets rv32_i --instructionSets rv_a --instructionSets rv_v --instructionSets Zve32x --instructionSets zvl1024b --cacheBlockBytes 32 --nPMPs 8 --cacheable 80000000-ffffffff --sideEffects 00000000-1fffffff --dcacheNSets 64 --dcacheNWays 4 --dcacheRowBits 32 --iCacheNSets 32 --iCacheNWays 4 --iCachePrefetch false --dLen 256 --vrfBankSize 2 --vrfRamType p0rp1w --instructionSets rv_c
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[t1rocket] update t1rocketemu TestBench.scala to build the config json
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[t1rocket] migrate difftest framework from t1 and update dpi from rocket
[t1rocket] refactor load_from_payload function to improve readability and performance [t1rocket] add elf crate dependency
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[t1rocket] add missing dependencies and fix some bugs
[t1rocket] add timeout check [t1rocket] use t1rocket_cosim_init instead of cosim_init to expose link bug
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[t1rocketemu] fix wrong mlirbc
Signed-off-by: Avimitin <[email protected]>
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Signed-off-by: Avimitin <[email protected]>
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[t1rocket] add online difftest
[t1rocket] fix wrong get_resetvector [t1rocket] fix unsafe extern "C" function signatures in dpi.rs [t1rocket] update axi_read_load_store function to use correct size parameter [t1rocket] add probes [t1rocket] add last commit cycle during axi to control timeout [t1rocket] add vrf score board check [t1rocket] refactor event's name in offline difftest
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[nix] refactor features set filter to be more structural
Signed-off-by: Avimitin <[email protected]>
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[nix] refactor test case to allow t1rocket attr opt-in
Signed-off-by: Avimitin <[email protected]>
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