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support zvk #731

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support zvk #731

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3 changes: 2 additions & 1 deletion configgen/generated/blastoise.json
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Original file line number Diff line number Diff line change
Expand Up @@ -167,7 +167,8 @@
]
]
],
"zvbbModuleParameters": []
"zvbbModuleParameters": [],
"zvkModuleParameters": []
}
},
"generator": "org.chipsalliance.t1.rtl.T1"
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3 changes: 2 additions & 1 deletion configgen/generated/machamp.json
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Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,8 @@
]
],
"floatModuleParameters": [],
"zvbbModuleParameters": []
"zvbbModuleParameters": [],
"zvkModuleParameters": []
}
},
"generator": "org.chipsalliance.t1.rtl.T1"
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20 changes: 19 additions & 1 deletion configgen/generated/psyduck.json
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,8 @@
"dLen": 256,
"extensions": [
"Zve32f",
"Zvbb"
"Zvbb",
"Zvk"
],
"t1customInstructions": [],
"vrfBankSize": 1,
Expand Down Expand Up @@ -184,6 +185,23 @@
3
]
]
],
"zvkModuleParameters": [
[
{
"parameter": {
"datapathWidth": 32,
"latency": 3
},
"generator": "org.chipsalliance.t1.rtl.LaneZvk"
},
[
0,
1,
2,
3
]
]
]
}
},
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3 changes: 2 additions & 1 deletion configgen/generated/sandslash.json
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Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,8 @@
]
],
"floatModuleParameters": [],
"zvbbModuleParameters": []
"zvbbModuleParameters": [],
"zvkModuleParameters": []
}
},
"generator": "org.chipsalliance.t1.rtl.T1"
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17 changes: 11 additions & 6 deletions configgen/src/Main.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -102,14 +102,15 @@ object Main {
),
floatModuleParameters =
Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))),
zvbbModuleParameters = Seq()
zvbbModuleParameters = Seq(),
zvkModuleParameters = Seq(),
)
)
if (doEmit) param.emit(targetFile)
param
}

// DLEN256 VLEN256; FP; VRF p0rw,p1rw bank1; LSU bank8 beatbyte 8; Zvbb
// DLEN256 VLEN256; FP; VRF p0rw,p1rw bank1; LSU bank8 beatbyte 8; Zvbb; Zvk
@main def psyduck(
@arg(name = "target-file", short = 't') targetFile: os.Path,
@arg(name = "emit", short = 'e', doc = "emit config") doEmit: Boolean = true
Expand All @@ -119,7 +120,7 @@ object Main {
val param = T1Parameter(
vLen,
dLen,
extensions = Seq("Zve32f", "Zvbb"),
extensions = Seq("Zve32f", "Zvbb", "Zvk"),
t1customInstructions = Nil,
vrfBankSize = 1,
vrfRamType = RamType.p0rwp1rw,
Expand Down Expand Up @@ -155,7 +156,9 @@ object Main {
floatModuleParameters =
Seq((SerializableModuleGenerator(classOf[LaneFloat], LaneFloatParam(32, 3)), Seq(0, 1, 2, 3))),
zvbbModuleParameters =
Seq((SerializableModuleGenerator(classOf[LaneZvbb], LaneZvbbParam(32, 3)), Seq(0, 1, 2, 3)))
Seq((SerializableModuleGenerator(classOf[LaneZvbb], LaneZvbbParam(32, 3)), Seq(0, 1, 2, 3))),
zvkModuleParameters =
Seq((SerializableModuleGenerator(classOf[LaneZvk], LaneZvkParam(128, 3)), Seq(0, 1, 2, 3)), (SerializableModuleGenerator(classOf[LaneZvk256], LaneZvkParam(256, 3)), Seq(0, 1, 2, 3))),
)
)
if (doEmit) param.emit(targetFile)
Expand Down Expand Up @@ -207,7 +210,8 @@ object Main {
)
),
floatModuleParameters = Seq(),
zvbbModuleParameters = Seq() // TODO
zvbbModuleParameters = Seq(),
zvkModuleParameters = Seq(),
)
)
if (doEmit) param.emit(targetFile)
Expand Down Expand Up @@ -259,7 +263,8 @@ object Main {
)
),
floatModuleParameters = Seq(),
zvbbModuleParameters = Seq() // TODO
zvbbModuleParameters = Seq(),
zvkModuleParameters = Seq(),
)
)
if (doEmit) param.emit(targetFile)
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2 changes: 1 addition & 1 deletion ipemu/src/TestBench.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -260,7 +260,7 @@ class TestBench(generator: SerializableModuleGenerator[T1, T1Parameter])
laneProbes.flatMap(laneProbe =>
laneProbe.slots.map(slot => slot.writeTag === tag.U && slot.writeQueueEnq && slot.writeMask.orR)
) ++ laneProbes.flatMap(laneProbe =>
laneProbe.crossWriteProbe.map(cp => cp.bits.writeTag === tag.U && cp.valid && cp.bits.writeMask.orR)
laneProbe.crossWriteProbe.map(cp => cp.bits.writeTag === tag.U && cp.valid && cp.bits.writeMask.orR) // TODO: zvkCrossWriteProbe
) ++
// vrf write from lsu
lsuProbe.slots.map(slot => slot.dataInstruction === tag.U && slot.writeValid && slot.dataMask.orR) ++
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3 changes: 3 additions & 0 deletions t1/src/Bundles.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -591,8 +591,11 @@ class ExecutionUnitRecord(parameter: LaneParameter)(isLastSlot: Boolean) extends
val maskForFilter: UInt = UInt(4.W)
// false -> lsb of cross read group
val executeIndex: Bool = Bool()
val zvkExecuteIndex: Option[UInt] = Option.when(parameter.zvkEnable)(UInt(2.W))
val source: Vec[UInt] = Vec(3, UInt(parameter.datapathWidth.W))
val crossReadSource: Option[UInt] = Option.when(isLastSlot)(UInt((parameter.datapathWidth * 2).W))
val zvkCrossReadSource: Option[UInt] =
Option.when(isLastSlot && parameter.zvkEnable)(UInt((parameter.datapathWidth * 4).W))

/** groupCounter need use to update `Lane.maskFormatResultForGroup` */
val groupCounter: UInt = UInt(parameter.groupNumberBits.W)
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