fixing after rebase

chipsalliance · May 21, 2021 · 565ee92 · 565ee92
1 parent eca3df1
commit 565ee92
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Showing 2 changed files with 1 addition and 1 deletion.
diff --git a/verilog/analysis/verilog_linter_test.cc b/verilog/analysis/verilog_linter_test.cc
@@ -941,6 +941,7 @@ TEST_F(ViolationFixerTest, PrintAppliedFixes) {
           "  wire a;   \n"
           "endmodule\n",
       });
+}
 
 TEST(VerilogLinterDocumentationTest, AllRulesMarkdownWithCustomCitations) {
   std::ostringstream stream;

diff --git a/verilog/tools/lint/BUILD b/verilog/tools/lint/BUILD
@@ -227,7 +227,6 @@ cc_binary(
     visibility = ["//visibility:public"],
     deps = [
         "//common/util:enum_flags",
-        "//common/util:file_util",
         "//common/util:init_command_line",
         "//common/util:logging",
         "//common/util:file_util",