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Issues list

Formatter splits label from assertion on new line unnecessarily formatter Verilog code formatter issues
#2284 opened Oct 18, 2024 by hankhsu1996
Format failed in $monitor task when $stime is passed in formatter Verilog code formatter issues
#1587 opened Jan 7, 2023 by hankhsu1996
Net declaration syntax error rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1586 opened Jan 7, 2023 by hankhsu1996
Class inheritance syntax error rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).
#1577 opened Dec 31, 2022 by hankhsu1996
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