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[pull] master from verilator:master #633

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Feb 8, 2025
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fa1b112
Fix duplicate-named class variable equivalence (#5737).
wsnyder Jan 18, 2025
4954e76
Commentary: Changes update
wsnyder Jan 18, 2025
f4a01eb
Fix inlined expression with assignment under LHS of NBA (#5736) (#5740)
gezalore Jan 20, 2025
0507fb4
Improve hierarchical DPI wrapper scheduling performance (#2583) (#5734)
b-chmiel Jan 20, 2025
35fa0d0
Support integer atom type ports in `--hierarchical` (#5748)
b-chmiel Jan 24, 2025
bed9aa9
Internals: Cleanup std::string empty string constructors.
wsnyder Jan 22, 2025
d808000
Commentary
wsnyder Jan 22, 2025
d4f4fef
Fix `-j` ignored after `-f` (#5749).
wsnyder Jan 24, 2025
432d5f8
Internals: Cleanup some misnamed nodep's. No functional change.
wsnyder Jan 25, 2025
929e15f
Fix various round-trip Verilog output, including packed arrays
wsnyder Jan 25, 2025
7e6dd94
Commentary: Changes update
wsnyder Jan 25, 2025
6281385
Commentary/Internals: Sort option names. No functional change.
wsnyder Jan 25, 2025
694f2ff
Tests: renames
wsnyder Jan 25, 2025
05c7a3b
Optimize labels as final `if` block statements (#5744).
wsnyder Jan 25, 2025
98e40c8
Internals: Suppress vlSelf unused suppression when known used. No fun…
wsnyder Jan 25, 2025
001c098
Optimize empty function definition bodies (#5750).
wsnyder Jan 25, 2025
41bb54b
Add Makefile targets count to stats
wsnyder Jan 25, 2025
70c6651
Fix -Wno-subobject-linkage on GCC (#5754)
wsnyder Jan 25, 2025
bdcfc4e
Reduce verbosity under `--debug` default level
wsnyder Jan 25, 2025
61bfb6c
Remove `list`/`map` from keyword warnings.
wsnyder Jan 25, 2025
e2a6e19
Cleanup V3EmitMk report style
wsnyder Jan 25, 2025
a379382
Fix handling forced assigns in V3Life (#5757)
b-chmiel Jan 28, 2025
e0e164c
Internals: Optimize clearFired (#5753)
wsnyder Jan 30, 2025
6b41836
Support Unpacked Structures' Constrained Randomization (#5657) (#5759)
YilouWang Feb 3, 2025
5b65c15
Internals: Add datap cast functions (#5761)
mjeje Feb 5, 2025
283f6c7
Add `--preproc-token-limit` (#5768)
kbieganski Feb 7, 2025
ac659d5
Support VPI array accessors (#5612)
mjeje Feb 8, 2025
cc1133c
Apply 'make format'
Feb 8, 2025
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Fix duplicate-named class variable equivalence (verilator#5737).
wsnyder committed Jan 18, 2025

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This commit was signed with the committer’s verified signature. The key has expired.
Czaki Grzegorz Bokota
commit fa1b11252e606a2aa451755a9e27d1cd06acf5e9
1 change: 1 addition & 0 deletions Changes
Original file line number Diff line number Diff line change
@@ -33,6 +33,7 @@ Verilator 5.033 devel
* Fix segfault when only enum value referenced in package (#5714). [Dan Katz]
* Fix `BLKSEQ` on suspendable processes (#5722). [Krzysztof Bieganski, Antmicro Ltd.]
* Fix matching language extension options including dots.
* Fix duplicate-named class variable equivalence (#5737).


Verilator 5.032 2025-01-01
6 changes: 4 additions & 2 deletions src/V3AstInlines.h
Original file line number Diff line number Diff line change
@@ -188,15 +188,17 @@ bool AstVarRef::sameNode(const AstVarRef* samep) const {
if (varScopep()) {
return (varScopep() == samep->varScopep() && access() == samep->access());
} else {
return (selfPointer() == samep->selfPointer() && varp()->name() == samep->varp()->name()
&& access() == samep->access());
return (selfPointer() == samep->selfPointer()
&& classOrPackagep() == samep->classOrPackagep()
&& varp()->name() == samep->varp()->name() && access() == samep->access());
}
}
bool AstVarRef::sameNoLvalue(AstVarRef* samep) const {
if (varScopep()) {
return (varScopep() == samep->varScopep());
} else {
return (selfPointer() == samep->selfPointer()
&& classOrPackagep() == samep->classOrPackagep()
&& (!selfPointer().isEmpty() || !samep->selfPointer().isEmpty())
&& varp()->name() == samep->varp()->name());
}
18 changes: 18 additions & 0 deletions test_regress/t/t_class_eq.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2025 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

import vltest_bootstrap

test.scenarios('simulator')

test.compile(verilator_flags2=['--binary'])

test.execute()

test.passes()
32 changes: 32 additions & 0 deletions test_regress/t/t_class_eq.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2025 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t();

class A;
int num;
function new(int num);
this.num = num;
endfunction
endclass

class B;
static A obj = new(2);
endclass

class C;
static A obj = new(5);
endclass

initial begin
#1;
$display("Bobj=%p Cobj=%p eq=%p", B::obj, C::obj, (B::obj == C::obj));
if (B::obj == C::obj) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

endmodule