sdc: Add test for missing arguments in read_sdc command

Signed-off-by: Tomasz Michalak <[email protected]>

sdc-plugin/tests/Makefile

@@ -32,7 +32,9 @@ TESTS = abc9 \
 	period_check \
 	waveform_check \
 	period_format_check \
-	get_clocks
+	get_clocks \
+	sdc_errors_missing_arguments
+
 
 UNIT_TESTS = escaping
 
@@ -57,4 +59,6 @@ waveform_check_verify = true
 waveform_check_negative = 1
 period_format_check_verify = true
 period_format_check_negative = 1
+sdc_errors_missing_arguments_verify = tail -n 1 sdc_errors_missing_arguments/sdc_errors_missing_arguments.log | grep sdc_errors_missing_arguments.input.sdc:1 > /dev/null
+sdc_errors_missing_arguments_negative = 1
 get_clocks_verify = $(call diff_test,get_clocks,txt)

sdc-plugin/tests/sdc_errors_missing_arguments/sdc_errors_missing_arguments.input.sdc

@@ -0,0 +1 @@
+create_clock -period 10.0

sdc-plugin/tests/sdc_errors_missing_arguments/sdc_errors_missing_arguments.tcl

@@ -0,0 +1,13 @@
+yosys -import
+if { [info procs read_sdc] == {} } { plugin -i sdc }
+yosys -import  ;# ingest plugin commands
+
+read_verilog $::env(DESIGN_TOP).v
+read_verilog -specify -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v
+read_verilog -lib +/xilinx/cells_xtra.v
+hierarchy -check -auto-top
+# Start flow after library reading
+synth_xilinx -flatten -abc9 -nosrl -nodsp -iopad -run prepare:check
+
+# Read the design's timing constraints
+read_sdc $::env(DESIGN_TOP).input.sdc

sdc-plugin/tests/sdc_errors_missing_arguments/sdc_errors_missing_arguments.v

@@ -0,0 +1,66 @@
+// Copyright (C) 2020-2021  The SymbiFlow Authors.
+//
+// Use of this source code is governed by a ISC-style
+// license that can be found in the LICENSE file or at
+// https://opensource.org/licenses/ISC
+//
+// SPDX-License-Identifier:ISC
+
+module top (
+    input clk,
+    input clk2,
+    input [1:0] in,
+    output [5:0] out
+);
+
+  reg [1:0] cnt = 0;
+  wire clk_int_1, clk_int_2;
+  IBUF ibuf_proxy (
+      .I(clk),
+      .O(ibuf_proxy_out)
+  );
+  IBUF ibuf_inst (
+      .I(ibuf_proxy_out),
+      .O(ibuf_out)
+  );
+  assign clk_int_1 = ibuf_out;
+  assign clk_int_2 = clk_int_1;
+
+  always @(posedge clk_int_2) begin
+    cnt <= cnt + 1;
+  end
+
+  middle middle_inst_1 (
+      .clk(ibuf_out),
+      .out(out[2])
+  );
+  middle middle_inst_2 (
+      .clk(clk_int_1),
+      .out(out[3])
+  );
+  middle middle_inst_3 (
+      .clk(clk_int_2),
+      .out(out[4])
+  );
+  middle middle_inst_4 (
+      .clk(clk2),
+      .out(out[5])
+  );
+
+  assign out[1:0] = {cnt[0], in[0]};
+endmodule
+
+module middle (
+    input  clk,
+    output out
+);
+
+  reg [1:0] cnt = 0;
+  wire clk_int;
+  assign clk_int = clk;
+  always @(posedge clk_int) begin
+    cnt <= cnt + 1;
+  end
+
+  assign out = cnt[0];
+endmodule