- Chisel (Scala)
- SystemVerilog
- Verilog
- VHDL
- HLS-C
- C
- C++
- Python
- RISC-V RV32I Core (Chisel) with plans to make an out-of-order processor
- Cache Memory System (VHDL)
- Directory copy tool for backing up files onto drives (Python)
- TI Sub-1Gigahertz Shield w/ CC1310 making the device a SPI Slave for RF Send & Receive and GPIO expansion (C++: CCS)
- RISC-V RV32I (subset) multi-cycle & pipeline core (SystemVerilog)
- FPGA video & temperature reading system (Verilog/Python)
- MNIST CNN Accelerator on Pynq-Z2 board (HLS-C)
Please feel free to ask me reachout and discuss any of my current or past projects! [email protected]