cpu: require PGE and NX support

All platforms capable of virtualization support PGE and NX, so there is no reason to make these features optional in the SVSM code base. Signed-off-by: Jon Lange <[email protected]>
coconut-svsm · Jul 24, 2024 · ca6fea7 · ca6fea7
1 parent 33a191e
commit ca6fea7
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Showing 3 changed files with 11 additions and 14 deletions.
diff --git a/kernel/src/cpu/control_regs.rs b/kernel/src/cpu/control_regs.rs
@@ -24,10 +24,12 @@ pub fn cr4_init() {
 
     cr4.insert(CR4Flags::PSE); // Enable Page Size Extensions
 
-    if cpu_has_pge() {
-        cr4.insert(CR4Flags::PGE); // Enable Global Pages
-    }
+    // All processors that are capable of virtualization will support global
+    // page table entries, so there is no reason to support any processor that
+    // does not enumerate PGE capability.
+    assert!(cpu_has_pge(), "CPU does not support PGE");
 
+    cr4.insert(CR4Flags::PGE); // Enable Global Pages
     write_cr4(cr4);
 }
 

diff --git a/kernel/src/cpu/efer.rs b/kernel/src/cpu/efer.rs
@@ -36,9 +36,11 @@ pub fn write_efer(efer: EFERFlags) {
 pub fn efer_init() {
     let mut efer = read_efer();
 
-    if cpu_has_nx() {
-        efer.insert(EFERFlags::NXE);
-    }
+    // All processors that are capable of virtualization will support
+    // no-execute table entries, so there is no reason to support any processor
+    // that does not enumerate NX capability.
+    assert!(cpu_has_nx(), "CPU does not support NX");
 
+    efer.insert(EFERFlags::NXE);
     write_efer(efer);
 }
diff --git a/kernel/src/mm/pagetable.rs b/kernel/src/mm/pagetable.rs
@@ -6,7 +6,6 @@
 
 use crate::address::{Address, PhysAddr, VirtAddr};
 use crate::cpu::control_regs::write_cr3;
-use crate::cpu::features::{cpu_has_nx, cpu_has_pge};
 use crate::cpu::flush_tlb_global_sync;
 use crate::error::SvsmError;
 use crate::locking::{LockGuard, SpinLock};
@@ -57,13 +56,7 @@ pub fn paging_init_early(platform: &dyn SvsmPlatform, vtom: u64) -> ImmutAfterIn
 pub fn paging_init(platform: &dyn SvsmPlatform, vtom: u64) -> ImmutAfterInitResult<()> {
     init_encrypt_mask(platform, vtom.try_into().unwrap())?;
 
-    let mut feature_mask = PTEntryFlags::all();
-    if !cpu_has_nx() {
-        feature_mask.remove(PTEntryFlags::NX);
-    }
-    if !cpu_has_pge() {
-        feature_mask.remove(PTEntryFlags::GLOBAL);
-    }
+    let feature_mask = PTEntryFlags::all();
     FEATURE_MASK.reinit(&feature_mask)
 }