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stage1: add TD Partitioning support #397

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merged 3 commits into from
Jul 17, 2024
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This set of patches enables TDX in stage1 trampoline-only mode. This includes bootstrapping from the reset vector in protected non-paged mode, performing sanity checks, and setting up the ESP register.

Since stage1.lds always designates to_pm_mode to 0xfffffe00, there is no
need to use relative addressing from 0xfffffe00. Use the symbol's
absolute address directly instead, when possible, to simplify reset.S.

Signed-off-by: Peter Fang <[email protected]>
TD CPUs always start execution in protected (32-bit) non-paged mode at
the reset vector. Add the code necessary for a vCPU to run in the
resetvector section directly in 32-bit mode. Since there is no need for
a TD CPU to transition to 32-bit mode, it takes a slightly simpler path
to reach startup_32. TD CPUs are initialized with a flat 32-bit code
segment so absolute addressing can be used.

Signed-off-by: Peter Fang <[email protected]>
Since TDP is the only platform right now that uses stage1-trampoline,
only allow platform type TDP when in trampoline-only mode. All TD vCPUs
start execution in 32-bit mode concurrently and therefore only TD BSP is
allowed to use the stage2 stack. Set vtom in Stage2LaunchInfo based on
the initial value of %ebx (GPAW).

Program an invalid address (0x7ffff000) into a TD AP's ESP register.
This address is chosen because a) it is most likely not an MMIO address
and b) it is an unaccepted page if it's backed by memory.

Signed-off-by: Peter Fang <[email protected]>
@00xc 00xc merged commit cd733a4 into coconut-svsm:main Jul 17, 2024
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@peterfang peterfang deleted the dev-tdp-stage1 branch July 17, 2024 22:57
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3 participants