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td-shim: Migration build ResetVector.bin
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Signed-off-by: haowx <weix.hao.intel.com>
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haowx committed Mar 17, 2022
1 parent f41adbf commit d7e3dde
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7 changes: 7 additions & 0 deletions td-shim/.gitignore
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*~

# Cargo Junk
Cargo.lock
target/
*.bin
*.obj
58 changes: 58 additions & 0 deletions td-shim/Cargo.toml
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[package]
name = "td-shim"
version = "0.1.0"
edition = "2018"

# add build process
build = "build.rs"

[build-dependencies]
anyhow = "1.0.55"
cc = { git = "https://github.com/jyao1/cc-rs.git", branch = "uefi_support" }
td-layout = { path = "../td-layout" }
tdx-tdcall = { path = "../tdx-tdcall" }
which = "4.2.4"

[dependencies]
lazy_static = { version = "1.4.0", features = ["spin_no_std"] }
log = "0.4.13"
r-efi = "3.2.0"
scroll = { version = "0.10", default-features = false, features = ["derive"] }
td-layout = { path = "../td-layout" }
td-uefi-pi = { path = "../td-uefi-pi" }
zerocopy = "0.6.0"

td-loader = { path = "../td-loader", optional = true }
linked_list_allocator = { version = "0.9.0", optional = true }
ring = { git = "https://github.com/jyao1/ring.git", branch = "uefi_support", default-features = false, features = ["alloc"], optional = true }
spin = { version = "0.9.2", optional = true }
td-exception = { path = "../td-exception", features = ["tdx"], optional = true }
td-logger = { path = "../td-logger", optional = true }
td-paging = { path = "../td-paging", optional = true }
x86 = { version ="0.44.0", optional = true }
# Lock down to 0.44, otherwise it depends on inline asm
x86_64 = { version = "=0.14.6", optional = true }

# secure boot
der = {version = "0.4.5", features = ["derive", "alloc"], optional = true}

# TDX
tdx-tdcall = { path = "../tdx-tdcall", optional = true }

[features]
default = ["boot-kernel", "cet-ss", "secure-boot"]
boot-kernel = ["td-layout/boot-kernel"]
cet-ss = []
secure-boot = ["der"]
tdx = ["tdx-tdcall", "td-exception/tdx", "td-logger/tdx", "x86"]
main = [
"td-loader",
"linked_list_allocator",
"ring",
"spin",
"td-exception",
"td-logger",
"td-paging",
"x86",
"x86_64",
]
4 changes: 4 additions & 0 deletions td-shim/ResetVector/.gitignore
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*~

# Bin Junk
*.bin
204 changes: 204 additions & 0 deletions td-shim/ResetVector/CommonMacros.inc
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;------------------------------------------------------------------------------
; @file
; Common macros used in the ResetVector VTF module.
;
; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------

%macro tdcall 0
%if (USE_TDX_EMULATION != 0)
vmcall
%else
db 0x66,0x0f,0x01,0xcc
%endif
%endmacro


%define ADDR16_OF(x) (0x10000 - fourGigabytes + x)
%define ADDR_OF(x) (0x100000000 - fourGigabytes + x)

%macro OneTimeCall 1
jmp %1
%1 %+ OneTimerCallReturn:
%endmacro

%macro OneTimeCallRet 1
jmp %1 %+ OneTimerCallReturn
%endmacro


CommandOffset equ 00h
ApicidOffset equ 04h
WakeupVectorOffset equ 08h
OSArgsOffset equ 10h
FirmwareArgsOffset equ 800h
WakeupArgsRelocatedMailBox equ 800h
ApWorkingStackStart equ 800h
CpuArrivalOffset equ 900h
CpusExitingOffset equ 0a00h
TalliesOffset equ 0a08h

MpProtectedModeWakeupCommandNoop equ 0
MpProtectedModeWakeupCommandWakeup equ 1
MpProtectedModeWakeupCommandSleep equ 2
MpProtectedModeWakeupCommandAssignWork equ 3
MpProtectedModeWakeupCommandCheck equ 4

MailboxApicIdInvalid equ 0xffffffff
MailboxApicidBroadcast equ 0xfffffffe

%macro simple_spinlock 3
mov edx, %1
mov eax, 0
mov ebx, 1
%%testlock:
lock cmpxchg [edx], ebx
jnz %3
mov eax, 0
mov ebx, 1
lock cmpxchg [edx+4], ebx
jnz %2
%%firstone:
pause
%endmacro

%macro simple_releaselock 3
%2:
mov eax, 1
mov edx, %1
jmp %%testlock
%3:
pause
mov eax, 0
%%testlock:
mov ebx, 0
lock cmpxchg [edx], ebx
jnz %3
%endmacro


%define PAGE_PRESENT 0x01
%define PAGE_READ_WRITE 0x02
%define PAGE_USER_SUPERVISOR 0x04
%define PAGE_WRITE_THROUGH 0x08
%define PAGE_CACHE_DISABLE 0x010
%define PAGE_ACCESSED 0x020
%define PAGE_DIRTY 0x040
%define PAGE_PAT 0x080
%define PAGE_GLOBAL 0x0100
%define PAGE_2M_MBO 0x080
%define PAGE_2M_PAT 0x01000

%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
PAGE_ACCESSED + \
PAGE_DIRTY + \
PAGE_READ_WRITE + \
PAGE_PRESENT)

%define PAGE_PDP_ATTR (PAGE_ACCESSED + \
PAGE_READ_WRITE + \
PAGE_PRESENT)

%define PT_ADDR(Base,Offset) ((Base) + (Offset))

%macro clear_pagetables 1
mov ecx, 6 * 0x1000 / 4
xor eax, eax
%%clearloop:
mov dword[ecx * 4 + PT_ADDR (%1,0) - 4], eax
loop %%clearloop
%endmacro

%macro init_l4_l3_page_tables 2
;
; Top level Page Directory Pointers (1 * 512GB entry)
;
mov dword[PT_ADDR (%1,0)], PT_ADDR (%1,0x1000) + PAGE_PDP_ATTR
mov dword[PT_ADDR (%1,4)], %2

;
; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
;
mov dword[PT_ADDR (%1,0x1000)], PT_ADDR (%1,0x2000) + PAGE_PDP_ATTR
mov dword[PT_ADDR (%1,0x1004)], %2
mov dword[PT_ADDR (%1,0x1008)], PT_ADDR (%1,0x3000) + PAGE_PDP_ATTR
mov dword[PT_ADDR (%1,0x100C)], %2
mov dword[PT_ADDR (%1,0x1010)], PT_ADDR (%1,0x4000) + PAGE_PDP_ATTR
mov dword[PT_ADDR (%1,0x1014)], %2
mov dword[PT_ADDR (%1,0x1018)], PT_ADDR (%1,0x5000) + PAGE_PDP_ATTR
mov dword[PT_ADDR (%1,0x101C)], %2
%endmacro

%macro init_l2_page_tables 2
;
; Page Table Entries (2048 * 2MB entries => 4GB)
;
mov ecx, 0x800
%%loop:
mov eax, ecx
dec eax
shl eax, 21
add eax, PAGE_2M_PDE_ATTR
mov [ecx * 8 + PT_ADDR (%1,0x2000 - 8)], eax
mov dword[(ecx * 8 + PT_ADDR (%1,0x2000 - 8)) + 4], %2
loop %%loop
%endmacro

%macro initialize_page_tables 2
clear_pagetables %1
init_l4_l3_page_tables %1,%2
init_l2_page_tables %1,%2
%endmacro


%define EFI_HOB_TYPE_HANDOFF 0x0001
%define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002
%define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003
%define EFI_HOB_TYPE_GUID_EXTENSION 0x0004
%define EFI_HOB_TYPE_FV 0x0005
%define EFI_HOB_TYPE_CPU 0x0006
%define EFI_HOB_TYPE_MEMORY_POOL 0x0007
%define EFI_HOB_TYPE_FV2 0x0009
%define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A
%define EFI_HOB_TYPE_UEFI_CAPSULE 0x000B
%define EFI_HOB_TYPE_FV3 0x000C
%define EFI_HOB_TYPE_UNUSED 0xFFFE
%define EFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF

%define EFI_RESOURCE_SYSTEM_MEMORY 0x00000000
%define EFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001
%define EFI_RESOURCE_IO 0x00000002
%define EFI_RESOURCE_FIRMWARE_DEVICE 0x00000003
%define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 0x00000004
%define EFI_RESOURCE_MEMORY_RESERVED 0x00000005
%define EFI_RESOURCE_IO_RESERVED 0x00000006
%define EFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007

%define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001
%define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002
%define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004
%define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080

%define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400
%define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800
%define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000
%define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000


%define EFI_IO_ATTR (EFI_RESOURCE_ATTRIBUTE_PRESENT + \
EFI_RESOURCE_ATTRIBUTE_INITIALIZED + \
EFI_RESOURCE_ATTRIBUTE_TESTED + \
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE)

%define EFI_LOW_MEM_ATTR (EFI_RESOURCE_ATTRIBUTE_PRESENT + \
EFI_RESOURCE_ATTRIBUTE_INITIALIZED + \
EFI_RESOURCE_ATTRIBUTE_TESTED + \
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE + \
EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE + \
EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + \
EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE)

%define TDCALL_TDINFO 0x1
%define TDCALL_TDACCEPTPAGE 0x6
19 changes: 19 additions & 0 deletions td-shim/ResetVector/DebugDisabled.asm
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;------------------------------------------------------------------------------
; @file
; Debug disabled
;
; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------

BITS 16

%macro debugInitialize 0
;
; No initialization is required
;
%endmacro

%macro debugShowPostCode 1
%endmacro
52 changes: 52 additions & 0 deletions td-shim/ResetVector/Ia32/Flat32ToFlat64.asm
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;------------------------------------------------------------------------------
; @file
; Transition from 32 bit flat protected mode into 64 bit flat protected mode
;
; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;------------------------------------------------------------------------------

BITS 32

;
; Modified: EAX. ECX
;
Transition32FlatTo64Flat:

mov eax, cr4
bts eax, 5 ; enable PAE

;
; esp [6:0] holds gpaw, if it is at least 52 bits, need to set
; LA57 and use 5-level paging
;
mov ecx, esp
and ecx, 0x2f
cmp ecx, 52
jl .set_cr4
bts eax, 12
.set_cr4:
mov cr4, eax

mov ecx, ADDR_OF(TopLevelPageDirectory)
;
; if we just set la57, we are ok, if using 4-level paging, adjust top-level page directory
;
bt eax, 12
jc .set_cr3
add ecx, 0x1000
.set_cr3:
mov cr3, ecx

mov eax, cr0
bts eax, 31 ; set PG
mov cr0, eax ; enable paging

jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)
BITS 64
jumpTo64BitAndLandHere:

debugShowPostCode POSTCODE_64BIT_MODE

OneTimeCallRet Transition32FlatTo64Flat
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