Merge pull request #104 from cpldcpu/v2.6testing

V2.6testing

README.md

@@ -150,6 +150,9 @@ Release History
 	- Updated Arduino library archive
 	- Fixed an issue where the config include was not used
  	- Support for LGT8F 	
+- v2.6 2024/05/01
+    - Re-added support for reduced core AVR that was broken in v2.5. Thanks to @U-1F992 for testing
+    - Fixed location of ws2812_config.h 
 
 
 You can find the old V1 here: https://github.com/cpldcpu/light_ws2812/tree/v1.0
@@ -162,7 +165,7 @@ Tested Combinations AVR
 | ATtiny 85 (Standard Core )| X*      |  X     |         |       |  X   |    |
 | ATtiny 13 (Standard Core)|        |        |    X    |       |     |    |
 | ATmega 8 (Standard Core)|        |        |         |   X    |  X  |    |
-| ATtiny 10* (Reduced Core)| X*      |  X*     |         |       |     |    |
+| ATtiny 10 (Reduced Core)| X      |  X      |         |       |     |    |
 | ATmega 168 (Standard Core)|        |        |         |       |  X  |  X  |
 | ATmega 32u4 (Standard Core)|        |        |         |   X    |  X   |  X  |
 

light_ws2812_AVR/Light_WS2812/light_ws2812.c

@@ -4,10 +4,11 @@
 * Controls WS2811/WS2812/WS2812B RGB-LEDs
 * Author: Tim ([email protected])
 *
-* Jan 18th, 2014  v2.0b Initial Version
-* Nov 29th, 2015  v2.3  Added SK6812RGBW support
-* Nov 11th, 2023  v2.5  Added support for ports that cannot be addressed with "out"
+* Jan 18, 2014  v2.0b Initial Version
+* Nov 29, 2015  v2.3  Added SK6812RGBW support
+* Nov 11, 2023  v2.5  Added support for ports that cannot be addressed with "out"
 *                       Added LGT8F88A support
+* May 1, 2024   v2.6 Added support for reduced core AVRs
 *
 * License: GNU GPL v2+ (see License.txt)
 */
@@ -56,20 +57,20 @@ void ws2812_sendarray(uint8_t *data,uint16_t datlen)
 #define w_totalperiod 1250
 
 // Fixed cycles used by the inner loop
-#if defined(__LGT8F__)
+#if defined(__LGT8F__)     // LGT8F88A
 #define w_fixedlow    4
 #define w_fixedhigh   6
 #define w_fixedtotal  10   
-#else
+#elif __AVR_ARCH__ == 100  // reduced core AVR
+#define w_fixedlow    2
+#define w_fixedhigh   4
+#define w_fixedtotal  8   
+#else                      // all others
 #define w_fixedlow    3
 #define w_fixedhigh   6
 #define w_fixedtotal  10   
 #endif
 
-// // Fixed cycles used by the inner loop
-// #define w_fixedlow    2
-// #define w_fixedhigh   4
-// #define w_fixedtotal  8   
 
 // Insert NOPs to match the timing, if possible
 #define w_zerocycles    (((F_CPU/1000)*w_zeropulse          )/1000000)
@@ -125,7 +126,9 @@ void inline ws2812_sendarray_mask(uint8_t *data,uint16_t datlen,uint8_t maskhi)
 {
   uint8_t curbyte,ctr,masklo;
   uint8_t sreg_prev;
+#if __AVR_ARCH__ != 100  
   uint8_t *port = (uint8_t*) _SFR_MEM_ADDR(ws2812_PORTREG);
+#endif
 
   ws2812_DDRREG |= maskhi; // Enable output
 
@@ -146,7 +149,11 @@ void inline ws2812_sendarray_mask(uint8_t *data,uint16_t datlen,uint8_t maskhi)
     "       clt         \n\t"
 #endif
     "loop%=:            \n\t"
+#if __AVR_ARCH__ == 100     
+    "       out   %2,%3 \n\t"    //  '1' [01] '0' [01] - re
+#else
     "       st    X,%3 \n\t"    //  '1' [02] '0' [02] - re
+#endif
 
 #if (w1_nops&1)
 w_nop1
@@ -168,6 +175,10 @@ w_nop16
     "       brts  1f    \n\t"    //  '1' [04] '0' [03]
     "       st    X,%4  \n\t"    //  '1' [--] '0' [04] - fe-low
     "1:     lsl   %1    \n\t"    //  '1' [05] '0' [05]
+#elif __AVR_ARCH__ == 100     
+    "       sbrs  %1,7  \n\t"    //  '1' [03] '0' [02]
+    "       out   %2,%4 \n\t"    //  '1' [--] '0' [03] - fe-low
+    "       lsl   %1    \n\t"    //  '1' [04] '0' [04]    
 #else
     "       sbrs  %1,7  \n\t"    //  '1' [04] '0' [03]
     "       st    X,%4 \n\t"     //  '1' [--] '0' [05] - fe-low
@@ -188,9 +199,13 @@ w_nop16
 #if (w2_nops&16)
   w_nop16 
 #endif
+#if __AVR_ARCH__ == 100     
+    "       out   %2,%4 \n\t"    //  '1' [+1] '0' [+1] - fe-high
+#else
     "       brcc skipone%= \n\t"    //  '1' [+1] '0' [+2] - 
     "       st   X,%4      \n\t"    //  '1' [+3] '0' [--] - fe-high
     "skipone%=:               "     //  '1' [+3] '0' [+2] - 
+#endif    
 #if (w3_nops&1)
 w_nop1
 #endif
@@ -210,7 +225,12 @@ w_nop16
     "       dec   %0    \n\t"    //  '1' [+4] '0' [+3]
     "       brne  loop%=\n\t"    //  '1' [+5] '0' [+4]
     :	"=&d" (ctr)
+#if __AVR_ARCH__ == 100    
+    :	"r" (curbyte), "I" (_SFR_IO_ADDR(ws2812_PORTREG)), "r" (maskhi), "r" (masklo)
+#else    
     :	"r" (curbyte), "x" (port), "r" (maskhi), "r" (masklo)
+#endif  
+
     );
   }
 

light_ws2812_AVR/Makefile

@@ -6,12 +6,18 @@
 F_CPU = 16000000
 # DEVICE = attiny85
 DEVICE = atmega168p
+EXAMPLES  = RGB_blinky RGBW_blinky Chained_writes Rainbow
+
+# Uncomment this to build for attiny10. The rainbow example uses too much memory for Attiny10
+# F_CPU = 8000000
+# DEVICE = attiny10
+# EXAMPLES  = RGB_blinky RGBW_blinky Chained_writes 
+
 #
 # Tools:
 CC = avr-gcc
 
 LIB       = light_ws2812
-EXAMPLES  = RGB_blinky RGBW_blinky Chained_writes Rainbow
 DEP		  = ws2812_config.h Light_WS2812/light_ws2812.h
 
 CFLAGS = -g2 -I. -ILight_WS2812 -mmcu=$(DEVICE) -DF_CPU=$(F_CPU) 

light_ws2812_AVR/ws2812_config.h

@@ -0,0 +1,34 @@
+/*
+ * light_ws2812_config.h
+ *
+ * v2.4 - Nov 27, 2016
+ *
+ * User Configuration file for the light_ws2812_lib
+ *
+ */ 
+
+
+#ifndef WS2812_CONFIG_H_
+#define WS2812_CONFIG_H_
+
+///////////////////////////////////////////////////////////////////////
+// Define Reset time in µs. 
+//
+// This is the time the library spends waiting after writing the data.
+//
+// WS2813 needs 300 µs reset time
+// WS2812 and clones only need 50 µs
+//
+///////////////////////////////////////////////////////////////////////
+
+#define ws2812_resettime  300 
+
+///////////////////////////////////////////////////////////////////////
+// Define I/O pin
+///////////////////////////////////////////////////////////////////////
+
+
+#define ws2812_port B     // Data port 
+#define ws2812_pin  0     // Data out pin
+
+#endif /* WS2812_CONFIG_H_ */