GitHub workflow for gateware releases

.github/workflows/gateware-release.yml

@@ -0,0 +1,35 @@
+name: gateware-release
+
+on:
+  push:
+    tags:
+      - gateware-*
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout source code
+        uses: actions/checkout@v3
+
+      - name: Install OSS CAD Suite
+        uses: YosysHQ/setup-oss-cad-suite@v1
+        with:
+          # Yosys 0.24+1 7ad7b55 - Includes required support for packed arrays in packed structs.
+          osscadsuite-version: '2022-12-08'
+
+      - name: Build gateware
+        run: |
+          DISTDIR="reDIP-SID-${GITHUB_REF_NAME}"
+          mkdir $DISTDIR
+          make -C gateware
+          cp -p gateware/README.md gateware/flash.bat gateware/flash.sh gateware/redip_sid.bin $DISTDIR
+          tar -czvf $DISTDIR.tar.gz $DISTDIR
+          zip -r $DISTDIR.zip $DISTDIR
+
+      - name: Release
+        uses: softprops/action-gh-release@v1
+        with:
+          files: |
+            reDIP-SID*.tar.gz
+            reDIP-SID*.zip

gateware/Makefile

@@ -18,7 +18,8 @@ MOD = $(TOP).sv \
 	sid_core.sv \
 	sid_api.sv
 
-ifdef MUACM
+MUACM ?= 0
+ifeq "$(MUACM)" "1"
 MOD += muacm.v
 FLG = -DMUACM
 endif
@@ -27,16 +28,19 @@ SRC = $(PKG) $(FUN) $(MOD)
 
 all: $(TOP).bin
 
-ifeq "$(SV2V)" "0"
-$(TOP).json: $(SRC) Makefile
-	yosys -p 'read_verilog -sv $(FLG) $(PKG) $(MOD); synth_ice40 -abc9 -device u -dff -top $(TOP) -json $@'
-else
+SV2V ?= 0
+ifeq "$(SV2V)" "1"
+# For Yosys < 0.24
 $(TOP).json: $(TOP).v
 	yosys -p 'read_verilog -sv $<; synth_ice40 -abc9 -device u -dff -top $(TOP) -json $@'
-endif
 
 $(TOP).v: $(SRC) Makefile
 	sv2v -E always -E assert -E logic -E unbasedunsized -w $@ -DYOSYS $(FLG) $(PKG) $(MOD)
+else
+# For Yosys >= 0.24
+$(TOP).json: $(SRC) Makefile
+	yosys -p 'read_verilog -sv $(FLG) $(PKG) $(MOD); synth_ice40 -abc9 -device u -dff -top $(TOP) -json $@'
+endif
 
 %.asc: %.json %.pcf
 	nextpnr-ice40 --up5k --package sg48 --freq 24 --json $*.json --pcf $*.pcf --asc $@
@@ -45,7 +49,7 @@ $(TOP).v: $(SRC) Makefile
 	icepack $< $@
 
 prog: $(TOP).bin
-	dfu-util -a 0 -D $< -R
+	dfu-util -d 1d50:6159,:6156 -a 0 -D $< -R
 
 sim:
 	verilator --Mdir sim_trace --timescale "1ns / 1ns" --trace-fst --trace-structs --trace-underscore --clk clk --cc -O3 -CFLAGS "-Wall" --x-assign fast --x-initial fast --noassert --exe --build sid_pkg.sv sid_api.sv --top sid_api sid_api_sim.cpp

gateware/README.md

@@ -0,0 +1,51 @@
+# reDIP SID Gateware
+
+## Description
+
+The reDIP SID FPGA gateware provides high quality SID emulation for
+the [reDIP SID](https://github.com/daglem/reDIP-SID) hardware.
+
+The gateware owes its existence to [reSID](https://github.com/daglem/reSID),
+the [SID internals documentation](https://github.com/libsidplayfp/SID_schematics/wiki)
+by Leandro "drfiemost" Nini and Dieter "ttlworks" Mueller, auxiliary code and
+guidance from Sylvain "tnt" Munaut, and a lot of work :-)
+
+The gateware implements cycle accurate emulation of the SID digital
+logic, and quite a few SID analog peculiarities. In order to make
+reasonably accurate emulation of some of these fit in the iCE40UP5K
+FPGA, a few novelties have been invented:
+
+* Combined sawtooth/triangle and pulse/sawtooth/triangle waveforms without lookup tables.
+* MOS6581 waveform, envelope, and filter cutoff DAC emulation without lookup tables.
+* Parameterizable filter cutoff curves requiring only a single 16kbit lookup table.
+
+By default, a single MOS6581 chip is emulated. The gateware also
+implements MOS8580 emulation and simultaneous emulation of two chips,
+however runtime configuration of these features are not yet
+implemented.
+
+## Installation
+
+The gateware may be installed on the reDIP SID hardware via USB using
+[dfu-util](https://dfu-util.sourceforge.net/):
+
+* Power down the board.
+* Keep the user button pressed while powering up the board.
+* Release the user button once the green LED starts blinking.
+* Install the gateware with `./flash.sh` (Linux / Mac OS) or `flash.bat` (Windows).
+
+## License
+
+This gateware is part of reDIP SID, a MOS 6581/8580 SID FPGA emulation platform.
+Copyright (C) 2022  Dag Lem \<[email protected]\>
+
+The source describes Open Hardware and is licensed under the CERN-OHL-S v2.
+
+You may redistribute and modify the source and make products using it under
+the terms of the [CERN-OHL-S v2](https://ohwr.org/cern_ohl_s_v2.txt).
+
+This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,
+INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A
+PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable conditions.
+
+Source location: [https://github.com/daglem/reDIP-SID](https://github.com/daglem/reDIP-SID)

gateware/flash.bat

@@ -0,0 +1 @@
+dfu-util.exe -d 1d50:6159,:6156 -a 0 -D redip_sid.bin -R

gateware/flash.sh

@@ -0,0 +1,3 @@
+#!/bin/sh
+
+dfu-util -d 1d50:6159,:6156 -a 0 -D redip_sid.bin -R